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EEWA: Energy-Efficient Workload-Aware Task Scheduling in Multi-core Architectures EEWA:多核架构中节能的工作负载感知任务调度
2014 IEEE International Parallel & Distributed Processing Symposium Workshops Pub Date : 2014-05-19 DOI: 10.1109/IPDPSW.2014.75
Quan Chen, Long Zheng, M. Guo, Zhiyi Huang
{"title":"EEWA: Energy-Efficient Workload-Aware Task Scheduling in Multi-core Architectures","authors":"Quan Chen, Long Zheng, M. Guo, Zhiyi Huang","doi":"10.1109/IPDPSW.2014.75","DOIUrl":"https://doi.org/10.1109/IPDPSW.2014.75","url":null,"abstract":"Modern multi-core architectures offer Dynamic Voltage and Frequency Scaling (DVFS) that can dynamically adjust the operating frequency of each core for energy saving. However, current parallel programming environments and schedulers for task-based programs do not utilize DVFS and thus suffer from energy inefficiency in multi-core processors. To reduce energy consumption while keeping high performance, this paper proposes an Energy-Efficient Workload-Aware (EEWA) task scheduler that is comprised of a workload-aware frequency adjuster and a preference-based task-stealing scheduler. Using DVFS, the workload-aware frequency adjuster can properly tune the frequencies of the cores according to the workload information of the tasks collected with online profiling. The preference-based task-stealing scheduler can then effectively balance the workloads among cores by stealing tasks according to a preference list. Experimental results show that EEWA can reduce energy consumption of task-based programs up to 29.8% with a slight performance degradation compared with existing task schedulers.","PeriodicalId":153864,"journal":{"name":"2014 IEEE International Parallel & Distributed Processing Symposium Workshops","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127976890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Service-Oriented Computing and Software Integration in Computing Curriculum 面向服务的计算与计算机课程中的软件集成
2014 IEEE International Parallel & Distributed Processing Symposium Workshops Pub Date : 2014-05-19 DOI: 10.1109/IPDPSW.2014.127
Yinong Chen, Zhizheng Zhou
{"title":"Service-Oriented Computing and Software Integration in Computing Curriculum","authors":"Yinong Chen, Zhizheng Zhou","doi":"10.1109/IPDPSW.2014.127","DOIUrl":"https://doi.org/10.1109/IPDPSW.2014.127","url":null,"abstract":"Web software development and cloud computing based on Service-Oriented Architecture (SOA) represent the latest parallel distributed computing theories, practices, and technologies. As a distributed software development diagram, SOA is being taught in many computer science programs. We do not suggest using SOA to replace the currently taught Object-Oriented Computing paradigm. As SOA is based on Object-Oriented Computing, we suggest teaching SOA as the continuation and extension. At Arizona State University, SOA paradigm is incorporated into our Computing Science program since 2006. This paper presents the topics of the related courses and the open resources created for the courses, which are available for public accesses, including textbooks, lecture presentation slides, tests and assignments, software tools, and a repository of components, services and applications.","PeriodicalId":153864,"journal":{"name":"2014 IEEE International Parallel & Distributed Processing Symposium Workshops","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117275351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Data Quality, Consistency, and Interpretation Management for Wind Farms by Using Neural Networks 基于神经网络的风电场数据质量、一致性和解释管理
2014 IEEE International Parallel & Distributed Processing Symposium Workshops Pub Date : 2014-05-19 DOI: 10.1109/IPDPSW.2014.55
A. Fuser, F. Fontaine, J. Copper
{"title":"Data Quality, Consistency, and Interpretation Management for Wind Farms by Using Neural Networks","authors":"A. Fuser, F. Fontaine, J. Copper","doi":"10.1109/IPDPSW.2014.55","DOIUrl":"https://doi.org/10.1109/IPDPSW.2014.55","url":null,"abstract":"The intermittent nature of wind poses significant problems to generation companies that wish to keep a close watch on the performance of their wind mills. A regular data mining process on historical measures becomes mandatory to analyze the behavior of each turbine, especially during periods of normal operation - that is when working regularly but with a possible loss of generation. GDF SUEZ has developed an innovative approach in order to recompute generations during suspicious periods by the use of a natural clustering method coupled with Neural Networks (NN) built from a huge genetic algorithm. This process, part of what is called Data Quality, Consistency and Interpretation Management (DQCIM), will be roughly depicted and intensively illustrated.","PeriodicalId":153864,"journal":{"name":"2014 IEEE International Parallel & Distributed Processing Symposium Workshops","volume":"200 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121312955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Parallelism Extraction Algorithm from Stream-Based Processing Flow Applying Spanning Tree 基于生成树的流处理流并行度提取算法
2014 IEEE International Parallel & Distributed Processing Symposium Workshops Pub Date : 2014-05-19 DOI: 10.1109/IPDPSW.2014.74
G. Wang, S. Yamagiwa, K. Wada
{"title":"Parallelism Extraction Algorithm from Stream-Based Processing Flow Applying Spanning Tree","authors":"G. Wang, S. Yamagiwa, K. Wada","doi":"10.1109/IPDPSW.2014.74","DOIUrl":"https://doi.org/10.1109/IPDPSW.2014.74","url":null,"abstract":"Manycore architecture promotes a massively parallel computing on the accelerators. Especially GPU is one of the main series of the high performance computing, which is also employed by top supercomputers in the world. The programming method on such accelerators includes development of a control program. The accelerator executes it to schedule the invocation timing of the accelerator's kernel program. The kernel program needs to be written based on the stream computing paradigm. Connecting I/Os of the kernel programs, we can develop a large application. When we consider the processing flow as a directed graph, we can implement a GUI-based programming tool for the accelerators. It visualizes a pipeline-based processing flow. However, it is very hard to find the starting point of a complex processing flow. Moreover, although the processing pipeline should include the potential parallelism, it is hard for the programmer to exploit it intuitively. This paper proposes an algorithm applying the spanning tree that mechanically exploits the parallelism and determines an execution order.","PeriodicalId":153864,"journal":{"name":"2014 IEEE International Parallel & Distributed Processing Symposium Workshops","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124114615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Teaching HDFS/MapReduce Systems Concepts to Undergraduates 向本科生教授HDFS/MapReduce系统概念
2014 IEEE International Parallel & Distributed Processing Symposium Workshops Pub Date : 2014-05-19 DOI: 10.1109/IPDPSW.2014.124
Linh Ngo, Edward B. Duffy, A. Apon
{"title":"Teaching HDFS/MapReduce Systems Concepts to Undergraduates","authors":"Linh Ngo, Edward B. Duffy, A. Apon","doi":"10.1109/IPDPSW.2014.124","DOIUrl":"https://doi.org/10.1109/IPDPSW.2014.124","url":null,"abstract":"This paper presents the development of a Hadoop MapReduce module that has been taught in a course in distributed computing to upper undergraduate computer science students at Clemson University. The paper describes our teaching experiences and the feedback from the students over several semesters that have helped to shape the course. We provide suggested best practices for lecture materials, the computing platform, and the teaching methods. In addition, the computing platform and teaching methods can be extended to accommodate emerging technologies and modules for related courses.","PeriodicalId":153864,"journal":{"name":"2014 IEEE International Parallel & Distributed Processing Symposium Workshops","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131953462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
ExCovery -- A Framework for Distributed System Experiments and a Case Study of Service Discovery 发现——分布式系统实验框架和服务发现案例研究
2014 IEEE International Parallel & Distributed Processing Symposium Workshops Pub Date : 2014-05-19 DOI: 10.1109/IPDPSW.2014.147
Andreas Dittrich, Stefan Wanja, M. Malek
{"title":"ExCovery -- A Framework for Distributed System Experiments and a Case Study of Service Discovery","authors":"Andreas Dittrich, Stefan Wanja, M. Malek","doi":"10.1109/IPDPSW.2014.147","DOIUrl":"https://doi.org/10.1109/IPDPSW.2014.147","url":null,"abstract":"Experiments are a fundamental part of science. They are needed when the system under evaluation is too complex to be analytically described and they serve to empirically validate hypotheses. This work presents the experimentation framework ExCovery for dependability analysis of distributed processes. It provides concepts that cover the description, execution, measurement and storage of experiments. These concepts foster transparency and repeatability of experiments for further sharing and comparison. ExCovery has been tried and refined in a manifold of dependability related experiments during the last two years. A case study is provided to describe service discovery (SD) as experiment process (EP). A working prototype for IP networks runs on the Distributed Embedded System (DES) wireless testbed at the Freie Universität Berlin.","PeriodicalId":153864,"journal":{"name":"2014 IEEE International Parallel & Distributed Processing Symposium Workshops","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131091504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
HMC-Sim: A Simulation Framework for Hybrid Memory Cube Devices HMC-Sim:混合存储立方体设备的仿真框架
2014 IEEE International Parallel & Distributed Processing Symposium Workshops Pub Date : 2014-05-19 DOI: 10.1142/S012962641442002X
John D. Leidel, Yong Chen
{"title":"HMC-Sim: A Simulation Framework for Hybrid Memory Cube Devices","authors":"John D. Leidel, Yong Chen","doi":"10.1142/S012962641442002X","DOIUrl":"https://doi.org/10.1142/S012962641442002X","url":null,"abstract":"The recent advent of stacked die memory and logic technologies has lead to a resurgence in research associated with fundamental architectural techniques. Many architecture research projects begin with ample simulation of the target theoretical functions and approach. However, the logical and physical nature three-dimensional stacked devices, such as the Hybrid Memory Cube (HMC) specification, fundamentally do not align with traditional memory simulation techniques. As such, there currently exists a chasm in the capabilities of modern architectural simulation frameworks. This work introduces a new simulation framework developed specifically for the Hybrid Memory Cube specification. We present a set of novel techniques implemented on an associated development framework that provide an infrastructure to flexibly simulate one or more Hybrid Memory Cube stacked die memory devices attached to an arbitrary core processor. The goal of this development infrastructure is to provide architectural simulation frameworks the ability to begin migrating current banked DRAM memory models to stacked HMC-based designs without a reduction in simulation fidelity or functionality. In addition to the core simulation architecture, this work also presents a series of memory workload test results using the infrastructure that elicit device, vault and bank utilization trace data from within a theoretical device. These evaluations have confirmed that HMC-Sim can provide insightful guidance in designing and developing highly efficient systems, algorithms, and applications, considering the next-generation three-dimensional stacked memory devices. HMC-Sim is currently open source, licensed under a BSD-style license and is freely available to the community.","PeriodicalId":153864,"journal":{"name":"2014 IEEE International Parallel & Distributed Processing Symposium Workshops","volume":"111 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131091903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
A Framework for Mapping Dynamic Virtual Kernels onto Heterogeneous Reconfigurable Platforms 一种将动态虚拟内核映射到异构可重构平台的框架
2014 IEEE International Parallel & Distributed Processing Symposium Workshops Pub Date : 2014-05-19 DOI: 10.1109/IPDPSW.2014.23
H. Sidiropoulos, K. Siozios, D. Soudris
{"title":"A Framework for Mapping Dynamic Virtual Kernels onto Heterogeneous Reconfigurable Platforms","authors":"H. Sidiropoulos, K. Siozios, D. Soudris","doi":"10.1109/IPDPSW.2014.23","DOIUrl":"https://doi.org/10.1109/IPDPSW.2014.23","url":null,"abstract":"Field Programmable Gate Arrays (FPGAs) promise a low power flexible alternative for today's market heterogeneous systems. In order to be widely accepted, novel solutions and approaches are required for fast and flexible application implementation. In this paper we propose a methodology, as well as the supporting toolflow targeting to provide fast implementation of multiple applications onto heterogeneous FPGAs. For this purpose we introduce the concept of dynamic virtual kernels. Experimental results prove the efficiency of the introduced solution, as we achieve application's mapping 30× faster on average compared to a state-of-art approach, with negligible performance degradation. Additionally, we enable the dynamic mapping of multiple applications onto a single FPGA with only a small penalty of 4.7% in the maximum operation frequency of those applications compared with our reference solution.","PeriodicalId":153864,"journal":{"name":"2014 IEEE International Parallel & Distributed Processing Symposium Workshops","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128335053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
CyGraph: A Reconfigurable Architecture for Parallel Breadth-First Search CyGraph:并行宽度优先搜索的可重构架构
2014 IEEE International Parallel & Distributed Processing Symposium Workshops Pub Date : 2014-05-19 DOI: 10.1109/IPDPSW.2014.30
Osama G. Attia, Tyler Johnson, Kevin Townsend, Phillip H. Jones, Joseph Zambreno
{"title":"CyGraph: A Reconfigurable Architecture for Parallel Breadth-First Search","authors":"Osama G. Attia, Tyler Johnson, Kevin Townsend, Phillip H. Jones, Joseph Zambreno","doi":"10.1109/IPDPSW.2014.30","DOIUrl":"https://doi.org/10.1109/IPDPSW.2014.30","url":null,"abstract":"Large-scale graph structures are considered as a keystone for many emerging high-performance computing applications in which Breadth-First Search (BFS) is an important building block. For such graph structures, BFS operations tends to be memory-bound rather than compute-bound. In this paper, we present an efficient reconfigurable architecture for parallel BFS that adopts new optimizations for utilizing memory bandwidth. Our architecture adopts a custom graph representation based on compressed-sparse raw format (CSR), as well as a restructuring of the conventional BFS algorithm. By taking maximum advantage of available memory bandwidth, our architecture continuously keeps our processing elements active. Using a commercial high-performance reconfigurable computing system (the Convey HC-2), our results demonstrate a 5× speedup over previously published FPGA-based implementations.","PeriodicalId":153864,"journal":{"name":"2014 IEEE International Parallel & Distributed Processing Symposium Workshops","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131723778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 59
Parallelization of the Trinity Pipeline for De Novo Transcriptome Assembly 从头转录组组装Trinity流水线的并行化
2014 IEEE International Parallel & Distributed Processing Symposium Workshops Pub Date : 2014-05-19 DOI: 10.1109/IPDPSW.2014.67
Vipin Sachdeva, C. Kim, K. E. Jordan, M. Winn
{"title":"Parallelization of the Trinity Pipeline for De Novo Transcriptome Assembly","authors":"Vipin Sachdeva, C. Kim, K. E. Jordan, M. Winn","doi":"10.1109/IPDPSW.2014.67","DOIUrl":"https://doi.org/10.1109/IPDPSW.2014.67","url":null,"abstract":"This paper details a distributed-memory implementation of Chrysalis, part of the popular Trinity workflow used for de novo transcripto me assembly. We have implemented changes to Chrysalis, which was previously multi-threaded for shared-memory architectures, to change it to a hybrid implementation which uses both MPI and OpenMP. With the new hybrid implementation, we report speedups of about a factor of twenty for both Graph From Fasta and Reads To Transcripts on an iDataPlex cluster for a sugar beet dataset containing around 130 million reads. Along with the hybrid implementation, we also use PyFasta to speed up Bowtie execution by a factor of three which is also part of the Trinity workflow. Overall, we reduce the runtime of the Chrysalis step of the Trinity workflow from over 50 hours to less than 5 hours for the sugar beet dataset. By enabling the use of multi-node clusters, this implementation is a significant step towards making de novo transcripto me assembly feasible for ever bigger transcripto me datasets.","PeriodicalId":153864,"journal":{"name":"2014 IEEE International Parallel & Distributed Processing Symposium Workshops","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123839500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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