2010 5th International Design and Test Workshop最新文献

Routability driven placement for mesh-based FPGA architecture 基于网格的FPGA架构的可路由性驱动布局

2010 5th International Design and Test Workshop Pub Date : 2010-12-14 DOI: 10.1109/IDT.2010.5724414

M. Turki, M. Abid, Z. Marrakchi, H. Mehrez

引用次数: 0

Soft-core reduction methodology for SIMD architecture: OPENRISC case study SIMD架构的软核缩减方法:OPENRISC案例研究

2010 5th International Design and Test Workshop Pub Date : 2010-12-01 DOI: 10.1109/IDT.2010.5724405

Bouthaina Damak, M. Baklouti, M. Abid

引用次数: 3

Voltage island design in multi-core SIMD processors 多核SIMD处理器中的电压岛设计

2010 5th International Design and Test Workshop Pub Date : 2010-12-01 DOI: 10.1109/IDT.2010.5724399

S. Majzoub

引用次数: 3

Identification of IR-drop hot-spots in defective power distribution network using TDF ATPG 利用TDF - ATPG识别故障配电网中的红外跌落热点

2010 5th International Design and Test Workshop Pub Date : 2010-12-01 DOI: 10.1109/IDT.2010.5724422

Junxia Ma, M. Tehranipoor, O. Sinanoglu, S. Almukhaizim

{"title":"Identification of IR-drop hot-spots in defective power distribution network using TDF ATPG","authors":"Junxia Ma, M. Tehranipoor, O. Sinanoglu, S. Almukhaizim","doi":"10.1109/IDT.2010.5724422","DOIUrl":"https://doi.org/10.1109/IDT.2010.5724422","url":null,"abstract":"As technology scales below 45nm and circuit integration density increases, power distribution network (PDN) contributes significantly to the total chip yield, escape, and reliability. Due to lack of controllability and observability, the PDN failure analysis has become extremely challenging. A robust PDN is essential to ensure the performance of circuits on-chip, especially for low power, high-speed designs. The area of PDN and the number of power vias and lines have dramatically increased in complex designs over the past several years resulting in increased defects on PDNs. In this paper, we present an efficient pattern generation flow that targets open defects on PDN. In this flow, the circuit layout is divided into smaller regions based on PDN structures. A vector-pair is generated to increase the region switching activity so that the gates will experience a larger-than-threshold IR-drop which may cause a timing or logic failure if only an open defect exists on power vias or power lines in that region. Various open defects on power/ground lines and vias are inserted and their impacts on circuit performance are investigated. A region sorting procedure is included in the proposed flow to reduce the computing effort. The proposed pattern generation and verification flow is implemented on ITC'99 benchmark circuit b19 and experimental results on open defect-induced IR-drop is presented and analyzed in this paper.","PeriodicalId":153183,"journal":{"name":"2010 5th International Design and Test Workshop","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123832771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

An automated design methodology for stress avoidance in analog & mixed signal designs 模拟和混合信号设计中避免应力的自动化设计方法

2010 5th International Design and Test Workshop Pub Date : 2010-12-01 DOI: 10.1109/IDT.2010.5724396

Romany Sameer, A. Mohieldin, H. Eissa

引用次数: 5

Cost-free low-power test in compression-based reconfigurable scan designs 基于压缩的可重构扫描设计的无成本低功耗测试

2010 5th International Design and Test Workshop Pub Date : 2010-12-01 DOI: 10.1109/IDT.2010.5724412

S. Almukhaizim, M. G. Mohammad, Eman AlQuraishi

{"title":"Cost-free low-power test in compression-based reconfigurable scan designs","authors":"S. Almukhaizim, M. G. Mohammad, Eman AlQuraishi","doi":"10.1109/IDT.2010.5724412","DOIUrl":"https://doi.org/10.1109/IDT.2010.5724412","url":null,"abstract":"Scan-based testing of integrated circuits produces significant switching activity during shift and capture operations, dissipating excessive power levels and, possibly, resulting in an unexpected behavior of the design. The problem is further accentuated in compression-based scan; as don't care bits are exploited to compress test patterns, additional care bits are specified in the deliverable pattern, limiting the effectiveness of x-filling techniques. In this work, we propose a low-power test method for compression-based reconfigurable scan architectures. In addition to their key objective of minimizing Test Data Volume (TDV), we illustrate how the distribution of care bits in scan chains can be manipulated, using the different encoding configurations supported by the reconfigurable scan architecture, with the objective of reducing the number of transitions during test. Hence, peak and average power of shift operation are effectively reduced. Experimental results, performed using one possible reconfigurable scan architecture as a case study, indicate that average and peak power may reduce by up to 33.8% and 26.7%, respectively, without affecting TDV and/or Test Application Time (TAT).","PeriodicalId":153183,"journal":{"name":"2010 5th International Design and Test Workshop","volume":"270 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125830537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Design and implementation of low latency network interface for network on chip 片上网络低延迟网络接口的设计与实现

2010 5th International Design and Test Workshop Pub Date : 2010-12-01 DOI: 10.1109/IDT.2010.5724404

Brahim Attia, Wissem Chouchene, A. Zitouni, Abid Nourdin, R. Tourki

引用次数: 13

Worst-case test vectors generation using genetic algorithms for the detection of total-dose induced leakage current failures 基于遗传算法的最坏情况测试向量生成方法用于总剂量感应泄漏电流故障检测

2010 5th International Design and Test Workshop Pub Date : 2010-12-01 DOI: 10.1109/IDT.2010.5724421

H. A. Abdel-Aziz, M. M. Abdel-Aziz, A. Wassal, A. Abou-Auf

引用次数: 0

On NOR-2 von Neumann multiplexing 关于NOR-2冯·诺伊曼复用

2010 5th International Design and Test Workshop Pub Date : 2010-12-01 DOI: 10.1109/IDT.2010.5724410

W. Ibrahim, Valeriu Beiu, A. Beg

引用次数: 2

Performance and bandwidth optimization for biological sequence alignment 生物序列比对的性能和带宽优化

2010 5th International Design and Test Workshop Pub Date : 2010-12-01 DOI: 10.1109/IDT.2010.5724429

L. Hasan, Z. Al-Ars, M. Taouil, K. Bertels

引用次数: 2