2006 11th International Symposium on Advanced Packaging Materials: Processes, Properties and Interface最新文献

{"title":"Well-Aligned Carbon Nanotubes for Device and Assembly Applications","authors":"L. Zhou, D. Hess, C. Wong","doi":"10.1109/ISAPM.2006.1666036","DOIUrl":"https://doi.org/10.1109/ISAPM.2006.1666036","url":null,"abstract":"The remarkable properties of carbon nanotubes (CNTs) with ballistic electrical transport and ultra high thermal conductivity have made them very attractive for microelectronic interconnects, thermal management and nanoscale device applications. This seminar discusses our recently developed CVD growth of well-aligned CNT films/arrays, their characterizations and applications related to microelectronics packaging. However, the high CNT growth temperature (>600 degC) and poor substrate adhesion impede the CNT implementation in microelectronics. To circumvent these obstacles for a successful CNT application, we propose using a CNT transfer technology process. The process is featured with a separation of the CNT growth and CNT to device assembly, which is enabled by an in-situ formed open-ended CNT structures that we have recently developed. This technique is similar to a flip-chip process and is compatible with current microelectronic device fabrication sequences and surface mount component assembly technology. Field emission testing of the as-assembled CNT devices indicates good field emission characteristics, with a field enhancement factor of 4540. In addition, we also demonstrate the creation of hierarchic structures (micro and nano-scaled) by controlled growth of CNTs for lotus effect (superhydrophobic) surfaces coatings and its geometric design and optimization are discussed. Aligned CNT prototypes for thermal management and electrical interconnect are also illustrated","PeriodicalId":151960,"journal":{"name":"2006 11th International Symposium on Advanced Packaging Materials: Processes, Properties and Interface","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124415543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effects of Barrier Layer on Copper-to-Silicon Diffusion and Intermetallic Compound Formation in Copper Wire Bonding","authors":"S. Zhang, C. Chen, R. Lee, A. Lau, P.P.H. Tsang, L. Mohamed, C. Chan, M. Dirkzwager","doi":"10.1109/ISAPM.2006.1665988","DOIUrl":"https://doi.org/10.1109/ISAPM.2006.1665988","url":null,"abstract":"Summary form only given. The conventional wire bonding has employed gold and aluminum wires as interconnection material for decades. With the requirements for high speed, high power and fine pitch applications, copper is emerging as the alternative bonding wires to replace gold and aluminum. In principle, copper has relatively good electrical mechanical and thermal properties. However, copper is known as a fast diffuser in silicon. The copper-to-silicon diffusion may cause the breakdown of IC devices. On the other hand, the bonding of copper wire on the aluminum pad will form intermetallic compound (IMC). The formation of Cu-Al IMC at the bonding interface may increase the electrical resistance and reduce the mechanical bonding strength. Therefore, in order to understand the long term reliability impact of copper wire bonding, it is necessary to investigate the aforementioned two issues. In a previous study, a preliminary investigation has been conducted to characterize the basic phenomena of copper-to-silicon diffusion and the formation of Cu-Al IMC. In this study, efforts will be made to investigate the effects of additional barrier layer on the diffusion and IMC growth phenomena in copper wire bonding. The barrier layer is a thin film of TiW between the aluminum bond pad and the silicon substrate. The purpose is to prevent the wire bond material from diffusing into the silicon. In the present investigation, two sets of specimens are fabricated for parallel study. One set is actual diode devices with wire bonding on aluminum pads. Another set is ideal lab specimens with thin film deposition on silicon substrates. The specimens have a layered structure of Cu/Al/TiW/Si. For benchmarking purpose, specimens with Cu/Al/Si, Au/Al/TiW/Si and Au/Al/Si are also prepared. These specimens are vacuum-sealed in glass tubes to prevent oxidation. A series of test program is arranged to anneal the samples at 175 deg C and 300 deg C. At various timing (from 1.5 hours to 400 hours) some specimens are taken out of the oven for the inspection of diffusion depth profiling and IMC formation by secondary ion mass spectrometry (SIMS) and scanning electron microscopy (SEM)/energy dispersive X-ray (EDX) on cross-section, respectively. The experimental results indicate that the TiW barrier layer can effectively prevent metal diffusion into the silicon. However, the side effect is that there will be more IMC growth at the Cu/Al and Au/Al interfaces. Besides, Cu-Al IMC is found to grow much slower than Au-Al IMC. The comparison between the ideal lab specimens and the actual diode chips shows similar trends in general. However, it seems that the Cu-to-Si diffusion in the diode chips is more severe than that in the ideal lab specimens. This phenomenon may be caused by certain processing conditions such as the wire bond pressure that may lead to excessive deformation of the aluminum pad. Detailed comparison and discussion of experimental results will be given in this paper","PeriodicalId":151960,"journal":{"name":"2006 11th International Symposium on Advanced Packaging Materials: Processes, Properties and Interface","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120871511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Packaging Trends and New Materials Challenges","authors":"H. Tong","doi":"10.1109/ISAPM.2006.1665989","DOIUrl":"https://doi.org/10.1109/ISAPM.2006.1665989","url":null,"abstract":"Summary form only given. In this presentation, I will summarize the system, IC and package trends in the microelectronics industry, and the accompanying new material challenges as the IC miniaturizes, more new systems are introduced to the market, and as a greater variety of new packages continues to be churned out at an ever-higher rate. Adding to the complexity are the ever-present low cost pressures, linking everything we do to cost from design to production, as well as the ever-more stringent \"green\" requirements placed on these new materials. All these translate to the needs to designing and producing the new materials under a new mindset and perhaps a new set of methodologies","PeriodicalId":151960,"journal":{"name":"2006 11th International Symposium on Advanced Packaging Materials: Processes, Properties and Interface","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125148127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Carbon Nanotube (CNT) Fins for Forced Convection Cooling of High Power Microprocessors","authors":"P. Bhattacharya, Y. Joshi, A. Fedorov, N. Bajwa, P. Ajayan","doi":"10.1109/ISAPM.2006.1666025","DOIUrl":"https://doi.org/10.1109/ISAPM.2006.1666025","url":null,"abstract":"Carbon nanotubes (CNTs) have been reported to have very high thermal conductivity, ranging from 700 W/m-K to 3000 W/m-K. However, there are not many heat transfer applications where these CNTs are used. The two main reasons behind this are that, it is hard to grow the CNTs up to a macroscopic height and it is difficult to achieve good thermal contact between the CNTs and the surface of the heat source. We have overcome both these problems and obtained CNT bundles as tall as 2.5 mm and with different cross sectional areas that can be arranged in an array on a metallic substrate. Thus, these CNT bundles can act as fins having very high thermal conductivity to remove much higher heat flux compared to fins of similar dimension and configuration made of the customary materials such as copper or aluminum. Our calculation shows that in forced air convection cooling, a performance enhancement of 2 to 3 times can be achieved using just 2 mm tall CNT bundle fins, compared to a commercially available aluminum or copper heat sink that can remove a heat flux of 20-30 W/cm2. That way we can achieve a better heat removal performance as well as a reduction in the size of the heatsink, without deviating much from the most convenient and widely used cooling technique","PeriodicalId":151960,"journal":{"name":"2006 11th International Symposium on Advanced Packaging Materials: Processes, Properties and Interface","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124093937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Simulation study of nanoparticle melting behavior for lead free nano solder application","authors":"H. Dong, K. Moon, Hongjin Jiang, C. Wong","doi":"10.1109/ISAPM.2006.1666010","DOIUrl":"https://doi.org/10.1109/ISAPM.2006.1666010","url":null,"abstract":"Summary form only given. Silver nanoparticle was used as model system for melting behavior study due to its wide application in the field of microelectronic packaging and the availability of force field. The embedded atom method (EAM) was employed in conjunction with molecular dynamics (MD) simulations to investigate the effect of particle size and temperature ramping up rate on nano silver melting behavior. Silver spheres with diameter of 10 nm and 4 nm were prepared, and the temperature was raised up to 1200 K at a ramping up rate of 0.1K/ps and 1K/ps respectively. [010] projection and pair correlation function (PCF) were applied to study the structural evolution of silver particles as temperature is ramping up. The melting point was derived by observing the abrupt increase in potential energy. The effect of particle size and temperature ramping up rate on melting point was investigated. Surface melting behavior was studied by comparing the micro-structure of silver atoms located in core/shell regions","PeriodicalId":151960,"journal":{"name":"2006 11th International Symposium on Advanced Packaging Materials: Processes, Properties and Interface","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122237512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Packaging Materials User in a New Era - Material & Packaging Solution Correspondent with Semiconductor","authors":"M. Mizuno","doi":"10.1109/ISAPM.2006.1666026","DOIUrl":"https://doi.org/10.1109/ISAPM.2006.1666026","url":null,"abstract":"With a higher integration of IC, advanced IC packages are evolving to various features. They are being required to be smaller and. thinner nevertheless the chips they contain being more fragile. For sustaining this evolution. Sumitomo Bakelite has provided a lot of packaging materials. Since the advanced 10 packages are assembled by using various kinds of materials, it becomes difficult to cope with the requirement by studying only a certain material. Furthermore, IC substrate is also required, to be thinner and multi-layered, securing a reliability of the inter layer connection is the first priority matter; Then we rather have to examine the most suitable combination of the materials. This keynote address describes the trend of advanced packages and our challenges to propose the total solution with the best combination of the packaging materials and IC substrate. An optical waveguide substrate as a foreseeing optelectronics generation is also surveyed","PeriodicalId":151960,"journal":{"name":"2006 11th International Symposium on Advanced Packaging Materials: Processes, Properties and Interface","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130090334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Lifetime prediction for advanced packaging based on physics of failure approaches on a micro and nano-scale","authors":"B. Wunderie, R. Dudek, D. Vogel, B. Michel","doi":"10.1109/ISAPM.2006.1665975","DOIUrl":"https://doi.org/10.1109/ISAPM.2006.1665975","url":null,"abstract":"Abstract form only given. Lifetime prediction for advanced packaging faces two challenges in the future: lifetime models for the nano-domain (material level) and consistent methodologies for a system approach. Either must incorporate a physics of failure based concept as well as simulative and experimental procedures to analyse failure mechanisms and describe them theoretically on different length scales and level of complexity and along with the necessary degree of detail. This requires new analytical methods on an experimental and computational level on the nano-side of the approach, new complexity-reduction concepts for a physics of failure scale-zooming description on the system side. The paper focuses on new results in the field of failure detection and residual stress measurements on micro-and nano-structures of electronic packages along with different modelling approaches like finite element and force field methods. Based on SAC solders the influence of micro-structure on creep and fatigue performance is demonstrated. Approaches for lifetime models for system reliability are presented describing competing failure mechanisms and are exemplified for flip-chip assemblies and power transistor packages","PeriodicalId":151960,"journal":{"name":"2006 11th International Symposium on Advanced Packaging Materials: Processes, Properties and Interface","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131096428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal Interface Material Resistance Measurement Apparatus","authors":"S. Badoni, J. Rhee","doi":"10.1109/ISAPM.2006.1666032","DOIUrl":"https://doi.org/10.1109/ISAPM.2006.1666032","url":null,"abstract":"It is well known that as the size of microprocessors decreases with respect to Moore's law, cooling issues have become more predominant and critical for the electronics industry. One source of thermal resistance requiring more characterization is thermal interface materials, TIMs. Thermal interface materials, such as greases, elastomeric pads, thermal tapes, phase change materials, gels, thermally conductive adhesives and solder, are used in a variety of electronic and microelectronic engineering applications. Currently in industry, TIM testers are modeled after ASTM D 5470, \"standard test method for steady-state thermal transmission properties of thermally conductive solid electrical insulation material\". ASTM D 5470 uses two metal blocks, one heated and one cooled, between which a TIM is placed. Temperature sensors are placed within the metal blocks. Since the temperature distribution is linear, the temperature of surface of the metal blocks in contact with the specimen can be calculated using the sensor-given temperatures and the distance between the sensors. A thermal model was also developed to ensure the placement of the thermocouples within uniform heat flow; this is especially critical for the thermocouple placed closest to the heater. A CPU cooling unit is used as a cooling mechanism and constant uniform pressure is maintained through the use of a pneumatic cylinder. Calibration and verification is done through the use of steel films. Phenolic and balsa wood insulate the copper rods ensuring one dimensional heat conduction","PeriodicalId":151960,"journal":{"name":"2006 11th International Symposium on Advanced Packaging Materials: Processes, Properties and Interface","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130850924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Optimal Parametric Design to Improve Chip Cooling","authors":"Y. Tseng, Hwai-Hui Fu, T. Hung, B. Pei","doi":"10.1109/ISAPM.2006.1666039","DOIUrl":"https://doi.org/10.1109/ISAPM.2006.1666039","url":null,"abstract":"In recent years, most electronic products were overcome the thermal problem by additional cooling equipments. These designs induce the manufacturing cost and the risk of the cooling failure problem. The present study utilizes Taguchi experimental design to speed up the investigation in the passive cooling design for electronic systems. A representative CFD (computational fluid dynamic) model has been selectively implemented to be a database for statistic analysis. Power density (A), orientation of mother board (B), chip geometry (C), opening between chips (D), and flow pattern (E) are the parameters selected in order to find out the optimal combination in thermal cooling with two-level statistical approach. The result indicates about 50% of effort in experiments or simulations could be saved. The results further verified that openings in the mother board, power density, and flow pattern are sequentially the important parameters and they do significantly influence the thermal behavior. Finally, the concept of opening not only improve the reliability but also reduce the manufacturing cost and simplify the assemble procedures","PeriodicalId":151960,"journal":{"name":"2006 11th International Symposium on Advanced Packaging Materials: Processes, Properties and Interface","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133125592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The Role of Superposition Techniques in Thermal Management","authors":"J. Rhee","doi":"10.1109/ISAPM.2006.1666038","DOIUrl":"https://doi.org/10.1109/ISAPM.2006.1666038","url":null,"abstract":"It is well-known that the performance and reliability of integrated circuits and other electronics are functions of operating temperature. The accurate prediction of temperature distributions for such applications poses engineering challenges due to many factors, including complex convection flows, non-uniform thermal boundary conditions, extrapolation to operation in extreme environments, and demanding steady-state and transient design requirements. In addition, the ever-increasing heat dissipation in a smaller package volume requires solutions with ever-increasing heat transfer and heat capacity. Thermal analysis and prediction based on superposition techniques are currently not as well-known as the use of numerical simulation tools readily available today. However, they are a powerful alternative to numerical simulation tools, especially for the complex scenarios that arise in this application. Superposition techniques can be applied to the design and interpretation of experiments and numerical simulations, and have the potential to form the building blocks of engineering tools that are more generally applicable to a wide range of challenging heat transfer problems","PeriodicalId":151960,"journal":{"name":"2006 11th International Symposium on Advanced Packaging Materials: Processes, Properties and Interface","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122137595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}