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A ZV-ZCS electrolytic capacitor-LessAC/DC isolated LED driver with continous energy regulation 一种ZV-ZCS电解电容-无ac /DC隔离连续能量调节LED驱动器
2016 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2016-03-20 DOI: 10.1109/APEC.2016.7467967
J. Lam, Nader A. El-Taweel
{"title":"A ZV-ZCS electrolytic capacitor-LessAC/DC isolated LED driver with continous energy regulation","authors":"J. Lam, Nader A. El-Taweel","doi":"10.1109/APEC.2016.7467967","DOIUrl":"https://doi.org/10.1109/APEC.2016.7467967","url":null,"abstract":"Conventional AC/DC LED drivers require a large energy storage capacitor at the output to provide a constant current to the LEDs. In order to minimize the size and cost of the driver circuit, electrolytic capacitors are conventionally used due to its high energy density and low cost. However, electrolytic capacitors are sensitive to operating temperature and have much shorter lifetime than the LED semiconductor devices, which significantly reduces the overall life time of the LED system. Another drawback with the current LED drivers is that the presence of the switching power losses restricts the use of high frequency operation, which results in using bulky passive circuit components in the drivers and significantly reduces the circuit power efficiency. This paper proposes a single-stage high power factor LED driver with almost zero switching losses and without the electrolytic capacitor. In the proposed circuit, discontinuous conduction mode (DCM) boost converter was utilized as a power factor correction (PFC) circuit, where it was integrated with an asymmetrical pulse width modulated (APWM) series resonant converter to form a single stage power conversion unit to drive the LEDs. The proposed circuit is able to achieve zero turn-on and turn-off switching operation and is able to eliminate the conventionally needed electrolytic capacitors by continuously regulating the DC-link voltage. The proposed LED driver was simulated and tested on a 12W design example to confirm that an almost unity power factor and an efficiency of 95% can be achieved.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130157341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Analysis and control of a reduced switch converter for active magnetic bearings 主动磁轴承减缩开关变换器的分析与控制
2016 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2016-03-20 DOI: 10.1109/APEC.2016.7468389
Dong Jiang, P. Kshirsagar
{"title":"Analysis and control of a reduced switch converter for active magnetic bearings","authors":"Dong Jiang, P. Kshirsagar","doi":"10.1109/APEC.2016.7468389","DOIUrl":"https://doi.org/10.1109/APEC.2016.7468389","url":null,"abstract":"A reduced switch converter for active magnetic bearing system is analyzed and its performance is experimentally validated at 24,000 rpm on a 4-axis magnetic bearing test-rig. Based on the coupled coil arrangement and unidirectional current operation, the reduced switch converter is derived and its modes of operation are elaborated. In comparison to conventional topologies, this converter reduces the requirement on number of switches, gate drives and pulse width modulation signals stemming from the controller. The analysis and experimental results successfully validates the operation of reduced switch converter to meet the magnetic bearing operation requirements.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134165577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Study and implementation of a high step-up voltage DC-DC converter using coupled-inductor and cascode techniques 利用耦合电感和级联编码技术研究和实现高升压DC-DC变换器
2016 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2016-03-20 DOI: 10.1109/APEC.2016.7468128
T. Liang, Yung-Ting Huang, Jian-Hsing Lee, Lo Pang-Yen Ting
{"title":"Study and implementation of a high step-up voltage DC-DC converter using coupled-inductor and cascode techniques","authors":"T. Liang, Yung-Ting Huang, Jian-Hsing Lee, Lo Pang-Yen Ting","doi":"10.1109/APEC.2016.7468128","DOIUrl":"https://doi.org/10.1109/APEC.2016.7468128","url":null,"abstract":"A novel high efficiency high step-up DC-DC converter is proposed in this paper. The proposed converter can achieve high voltage ratio with appropriate duty cycle by using the coupled-inductor and cascode technique. In order to achieve high efficiency, a capacitor is used to recycle the leakage energy of the coupled-inductor and reduce the voltage stress on the switch. Therefore, the low-voltage rating MOSFET with low conduction resistance can be used. The operational principles and steady-state analysis of the proposed converter are discussed in detail. Finally, a prototype circuit with input voltage 24 V, output voltage 200 V and output power 250 W is implemented to verify the performances of the proposed converter. The experimental results reveals that the highest efficiency of the proposed converter is 94.6%, the full load efficiency is 92.3%, and the 10% load efficiency is 93.8%.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131628533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Accurate parametric steady state analysis and design tool for DC-DC power converters 准确的参数稳态分析和设计工具的DC-DC电源变换器
2016 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2016-03-20 DOI: 10.1109/APEC.2016.7468228
Mohammad Daryaei, M. Ebrahimi, S. A. Khajehoddin
{"title":"Accurate parametric steady state analysis and design tool for DC-DC power converters","authors":"Mohammad Daryaei, M. Ebrahimi, S. A. Khajehoddin","doi":"10.1109/APEC.2016.7468228","DOIUrl":"https://doi.org/10.1109/APEC.2016.7468228","url":null,"abstract":"Accurate large signal analysis and modeling of Power Electronics converters are essential for achieving high performance and reliable designs. Converter topologies with large signal variations are conventionally analyzed using numerical methods, averaged or inaccurate analyses. In this paper, a mathematical theorem based on Laplace transform is developed to derive the steady state response of periodic signals with a switching input signal. It is shown that the proposed methodology provides accurate and parametric analysis tool for dc-dc power converters specially for resonant converters and has many applications in design and analysis of the converters and their control systems. The proposed method is used to analyze and model a few power circuit including full bridge Series Resonant Converter (SRC) topology where both CCM and DCM operating modes are analyzed. It is observed that the proposed analysis approach gives great insight and simplifies converter design. The proposed analysis and modeling approach is also validated by simulations and experimental results.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127564369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A new capacitance estimation method of supercapacitor bank using a bank impedance and current injection 提出了一种利用组阻抗和电流注入估算超级电容器组电容的新方法
2016 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2016-03-20 DOI: 10.1109/APEC.2016.7467920
Junwon Lee, Hyunsik Jo, H. Cha
{"title":"A new capacitance estimation method of supercapacitor bank using a bank impedance and current injection","authors":"Junwon Lee, Hyunsik Jo, H. Cha","doi":"10.1109/APEC.2016.7467920","DOIUrl":"https://doi.org/10.1109/APEC.2016.7467920","url":null,"abstract":"This paper proposes a capacitance estimation method of the supercapacitor bank in the supercapacitor energy storage system (SCESS). To diagnose a deterioration, the capacitance of the supercapacitor bank is estimated by using a current injection. The injected current causes an AC ripple voltage and AC ripple current in the supercapacitor bank, which are extracted by using the proposed signal processing method. The proposed method provides an accurate value of the capacitance for reliability and durability of the supercapacitor energy storage system. Usefulness of the proposed estimation method is verified through simulation and experiment with a prototype of a 10kW SCESS. Experimental results shows that the maximum estimation error rate is less than 3% at both 2.25F and 2.57F capacitance bank.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130965849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Iron loss evaluation of three-phase inductor for three-phase PWM inverter 三相PWM逆变器三相电感铁损评估
2016 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2016-03-20 DOI: 10.1109/APEC.2016.7467944
H. Matsumori, Toshihisa Shimizu, K. Takano, Ishii Hitoshi
{"title":"Iron loss evaluation of three-phase inductor for three-phase PWM inverter","authors":"H. Matsumori, Toshihisa Shimizu, K. Takano, Ishii Hitoshi","doi":"10.1109/APEC.2016.7467944","DOIUrl":"https://doi.org/10.1109/APEC.2016.7467944","url":null,"abstract":"The iron losses of three-phase inductor used in a three-phase pulse-width modulation (PWM) inverter are evaluated. First we clarify three-phase inductor design in order to make same inductance value between the each phase. Then based on the design, iron losses for various structure of inductor are simulated. Simulation result shows the iron loss can be reduced about 5% by changing structure from conventional structure. Finally, we create conventional type and newly designed inductor and measure iron loss on a real PWM inverter. In the experiment, iron loss can be reduced about 10% compared with conventional type. Furthermore the calculated agree with measured losses within 10%. The iron loss reduction is verified by simulation and experiment.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132912109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A three-level space vector modulation scheme for paralleled two converters to reduce zero-sequence circulating current and common mode voltage 一种用于并联两个变换器的三电平空间矢量调制方案，以减小零序循环电流和共模电压
2016 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2016-03-20 DOI: 10.1109/APEC.2016.7467871
Zhongyi Quan, Y. Li
{"title":"A three-level space vector modulation scheme for paralleled two converters to reduce zero-sequence circulating current and common mode voltage","authors":"Zhongyi Quan, Y. Li","doi":"10.1109/APEC.2016.7467871","DOIUrl":"https://doi.org/10.1109/APEC.2016.7467871","url":null,"abstract":"Circulating current has been the major concern for the implementing of paralleled converters. This paper proposes a three-level space vector modulation (SVM) scheme for the system constructed by two paralleled voltage source converters (VSCs) and common mode inductor (CMI). The proposed scheme aims to reduce the zero-sequence circulating current (ZSCC) and the magnitude of common mode voltage (CMV) of the system. The ZSCC pattern with respect to modulation schemes are first analyzed to provide a clear understanding of the generation of ZSCC. And then the proposed scheme is introduced. Analysis regarding the ZSCC peak value, impact on the common mode current (CMC), and switching losses are made and compared with the existing methods. The proposed method has been verified in simulation and experiment.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132274720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Equivalent circuit modeling of LLC resonant converter LLC谐振变换器等效电路建模
2016 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2016-03-20 DOI: 10.1109/APEC.2016.7468082
Shuilin Tian, F. Lee, Qiang Li
{"title":"Equivalent circuit modeling of LLC resonant converter","authors":"Shuilin Tian, F. Lee, Qiang Li","doi":"10.1109/APEC.2016.7468082","DOIUrl":"https://doi.org/10.1109/APEC.2016.7468082","url":null,"abstract":"LLC resonant converter is widely used in industry. However, up to now, no simple and accurate small-signal equivalent circuit model is available. This paper proposes an equivalent circuit model of LLC resonant converter. The simple equivalent circuit model is derived based on modification and simplification of extended describing function method. The model can well predicts the small-signal behaviors observed in LLC resonant converter, whenever switching frequency is below, close to or above the resonant frequency. For the first time, analytical expressions for control to output voltage, input to output voltage, input impedance and output impedance are provided to aid close loop feedback design. Simplis simulation and experimental results are presented to prove the accuracy of the model.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132759311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 80
Effects and analysis of minimum pulse width limitation on adaptive DC voltage control of grid converters 最小脉宽限制对电网变流器直流电压自适应控制的影响及分析
2016 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2016-03-20 DOI: 10.1109/APEC.2016.7468047
Bo Sun, I. Trintis, S. Munk‐Nielsen, J. Guerrero
{"title":"Effects and analysis of minimum pulse width limitation on adaptive DC voltage control of grid converters","authors":"Bo Sun, I. Trintis, S. Munk‐Nielsen, J. Guerrero","doi":"10.1109/APEC.2016.7468047","DOIUrl":"https://doi.org/10.1109/APEC.2016.7468047","url":null,"abstract":"This paper presents an adaptive dc-link voltage controller for the purpose of decreasing the operating dc-link voltage in a back-to-back converter system. An outer loop to control the maximum modulation (Mmax) index is added to the conventional dc-link voltage controller, and hence the system can online adapt its dc-link voltage reference based on the system operating state. Furthermore, the relationship between current THD, minimum pulse width limitation and Mmax index reference is analyzed in order to obtain an optimized performance of the system. Finally, the dynamic performance and analysis of controller is investigated by experimental results.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133148308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Off-line identification of digitally controlled power converters using an analog frequency response analyzer 使用模拟频响分析仪的数字控制电源变换器的离线识别
2016 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2016-03-20 DOI: 10.1109/APEC.2016.7468079
M. Meola, A. Kelly
{"title":"Off-line identification of digitally controlled power converters using an analog frequency response analyzer","authors":"M. Meola, A. Kelly","doi":"10.1109/APEC.2016.7468079","DOIUrl":"https://doi.org/10.1109/APEC.2016.7468079","url":null,"abstract":"The use of a digital architecture in PWM controllers for point-of-load (POL) applications, together with system identification techniques, allows the development of fully automated routines for in-situ system performance optimization where controller parameters are specifically tailored to the application. In this context, this paper proposes a method for performing parametric system identification of digitally controlled power converters using a conventional analog frequency response analyzer (FRA). Nonlinearities intrinsic to the digital loop are taken into account, thus leading to accurate estimation of converter parameters. The proposed method has been verified on a digitally controlled POL with Vin=12V, Vout=1.2V, Iout=10A and fsw=400kHz for various bulk capacitor scenarios.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128853525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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