2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)最新文献_第2页

Manufacturing of silver-ink micrometer inductors through multilayer D.O.D. printing for VHF Power Transfer 利用多层D.O.D.印刷制造用于甚高频功率传输的银墨微米电感

2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME) Pub Date : 2022-06-12 DOI: 10.1109/prime55000.2022.9816792

Giuseppe Barbalace, D. Natali, Martina Scolari

引用次数: 0

Logic Synthesis From Incomplete Specifications Using Disjoint Support Decomposition 基于不相交支持分解的不完全规范逻辑综合

2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME) Pub Date : 2022-06-12 DOI: 10.1109/prime55000.2022.9816806

Andrea Costamagna, G. Micheli

{"title":"Logic Synthesis From Incomplete Specifications Using Disjoint Support Decomposition","authors":"Andrea Costamagna, G. Micheli","doi":"10.1109/prime55000.2022.9816806","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816806","url":null,"abstract":"Approximate logic synthesis is an emerging field that tolerates errors in the synthesized logic circuits for better optimization quality. Indeed, in many computing problems, the requirement of preserving the exact functionality either results in unnecessary overuse of resources or is hardly possible to meet. The latter case is typical of incompletely specified synthesis problems, targeting the hardware implementation of a Boolean function from a partial knowledge of its care set. The missing elements of the care set are named don’t knows. Previous works identified information theory-based decomposition strategies as powerful synthesis tools. Nonetheless, the definition of an automatic method for approximate synthesis is an open problem, and the approximate counterpart of many logic synthesis techniques is still missing. In this paper, we extend a disjoint support decomposition algorithm to target Boolean functions in the presence of don’t knows. Furthermore, we integrate the decomposition in an information theory-based synthesis flow. Relative experiments on the IWLS2020 benchmarks show that, on average, the addition of the designed decomposition to the flow reduces by 15.81% the number of gates and by 9.66% the depth.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134145199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Analysis and Design of a Fully-Integrated Pulsed LiDAR Driver in 100V-GaN IC Technology 基于100V-GaN集成电路技术的全集成脉冲激光雷达驱动器分析与设计

2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME) Pub Date : 2022-06-12 DOI: 10.1109/prime55000.2022.9816827

A. Bettini, T. Cosnier, A. Magnani, O. Syshchyk, M. Borga, S. Decoutere, A. Neviani

引用次数: 1

An Ultra Low-Voltage RF Front-end Receiver for IoT Devices 物联网设备的超低电压射频前端接收器

2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME) Pub Date : 2022-06-12 DOI: 10.1109/prime55000.2022.9816813

F. Malena, X. Aragonès, D. Mateo, Michele Caselli, A. Boni

引用次数: 0

16- and 64-Point Analog Computing of FFT with Improved Performance and Efficiency 提高FFT性能和效率的16点和64点模拟计算

2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME) Pub Date : 2022-06-12 DOI: 10.1109/prime55000.2022.9816825

Jingjing Li, Xingchen Chao, Qiang Li

引用次数: 1

Electrical Model of a Wireless mW-Power and Mbps-Data Transfer System Over a Single Pair of Coils 单对线圈上无线毫瓦功率和mbps数据传输系统的电学模型

2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME) Pub Date : 2022-06-12 DOI: 10.1109/prime55000.2022.9816821

David Palomeque-Mangut, A. Schmid, Á. Rodríguez-Vázquez, M. Delgado-Restituto

{"title":"Electrical Model of a Wireless mW-Power and Mbps-Data Transfer System Over a Single Pair of Coils","authors":"David Palomeque-Mangut, A. Schmid, Á. Rodríguez-Vázquez, M. Delgado-Restituto","doi":"10.1109/prime55000.2022.9816821","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816821","url":null,"abstract":"This paper proposes a system to transfer both mW-power and Mbps-data over an inductive link using a single pair of coils. The system is able to handle a wide range of loads by implementing a load adapter block that divides the operation into two phases: a Power Transfer Phase (PTP) and a Data Transfer Phase (DTP). On the one hand, during PTP, a constant amount of power is drawn from the inductive link, regardless of the current demanded by the load. On the other hand, during DTP, the load is powered with external capacitors, allowing the inductive link to be used for data transmission. With this architecture, intended to be used in a neural implant, power can be delivered to a wide range of loads without affecting the uplink/downlink data communication reliability and with no need of extra coils. Thus, the proposed solution permits minimizing the overall size of the neural implant. An electrical mixed-signal model of the system is described and implemented in MATLAB Simulink through Simscape Electrical and Stateflow toolboxes. Simulations performed on the electrical model of the system are shown and discussed.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132148236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Runtime Reconfigurable Hardware Accelerator for Energy-Efficient Transposed Convolutions 运行时可重构硬件加速器节能转置卷积

2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME) Pub Date : 2022-06-12 DOI: 10.1109/prime55000.2022.9816800

Emanuel Marrazzo, F. Spagnolo, S. Perri

{"title":"Runtime Reconfigurable Hardware Accelerator for Energy-Efficient Transposed Convolutions","authors":"Emanuel Marrazzo, F. Spagnolo, S. Perri","doi":"10.1109/prime55000.2022.9816800","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816800","url":null,"abstract":"Transposed convolution is a crucial operation in several computer vision applications, including emerging Convolutional Neural Networks for super-resolution, generative adversarial and segmentation tasks. Such algorithms deal with high computational loads and memory requirements, which hinder their implementation in real-time and power-constrained embedded systems. In addition, they may adopt different kernel sizes along the network, thus making the design of flexible yet efficient hardware architectures highly desirable. This paper presents a reconfigurable accelerator able to runtime adapt its computational capabilities to perform transposed convolution with different kernel sizes. When accommodated within the Xilinx XC7Z020 and XC7K410T chips, the proposed design dissipates less than 95 mW at 125MHz and 179 mW at 250MHz, exhibiting a throughput of 1.95 and 3.9 Giga output per second, respectively. Both the implementations overcome state-of-the-art counterparts, achieving an energy efficiency up to 4.4 times higher. When used to accelerate the Fast Super Resolution Convolutional Neural Networks, the novel reconfigurable architecture achieves an energy efficiency at least 23% better than the competitors.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128853860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Design Algorithm for N-bit Input Parallel Counters in Application to dSiPM Readout 应用于dSiPM读出的n位输入并行计数器设计算法

2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME) Pub Date : 2022-06-12 DOI: 10.1109/prime55000.2022.9816803

Simone Giroletti, L. Ratti, C. Vacchi

引用次数: 0

Analysis of Current-Reuse and Split-Voltage Topology for Biomedical Amplifier Arrays 生物医学放大器阵列电流复用与分压拓扑分析

2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME) Pub Date : 2022-06-12 DOI: 10.1109/prime55000.2022.9816819

Sebastian Simmich, R. Rieger

引用次数: 0

CMOS driving circuit operating down to 77 K for single-photon emitting diode 用于单光子发射二极管的CMOS驱动电路，工作温度低至77k

2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME) Pub Date : 2022-06-12 DOI: 10.1109/prime55000.2022.9816818

Michele Castriotta, Alexander Falbo, Luca Orsenigo, Fabio Olivieri, G. Ferrari

引用次数: 0