Logic Synthesis From Incomplete Specifications Using Disjoint Support Decomposition

Abstract

Approximate logic synthesis is an emerging field that tolerates errors in the synthesized logic circuits for better optimization quality. Indeed, in many computing problems, the requirement of preserving the exact functionality either results in unnecessary overuse of resources or is hardly possible to meet. The latter case is typical of incompletely specified synthesis problems, targeting the hardware implementation of a Boolean function from a partial knowledge of its care set. The missing elements of the care set are named don’t knows. Previous works identified information theory-based decomposition strategies as powerful synthesis tools. Nonetheless, the definition of an automatic method for approximate synthesis is an open problem, and the approximate counterpart of many logic synthesis techniques is still missing. In this paper, we extend a disjoint support decomposition algorithm to target Boolean functions in the presence of don’t knows. Furthermore, we integrate the decomposition in an information theory-based synthesis flow. Relative experiments on the IWLS2020 benchmarks show that, on average, the addition of the designed decomposition to the flow reduces by 15.81% the number of gates and by 9.66% the depth.