Hardware and Architectural Support for Security and Privacy最新文献

Position Paper: Consider Hardware-enhanced Defenses for Rootkit Attacks 意见书:考虑硬件增强的Rootkit攻击防御

Hardware and Architectural Support for Security and Privacy Pub Date : 2020-10-17 DOI: 10.1145/3458903.3458909

Guangyuan Hu, Tianwei Zhang, Ruby B. Lee

引用次数: 0

FPGA Bitstream Modification with Interconnect in Mind 考虑互连的FPGA位流修改

Hardware and Architectural Support for Security and Privacy Pub Date : 2020-10-17 DOI: 10.1145/3458903.3458908

M. Moraitis, E. Dubrova

引用次数: 3

Analysis and Hardware Optimization of Lattice Post-Quantum Cryptography Workloads 点阵后量子加密工作负载分析与硬件优化

Hardware and Architectural Support for Security and Privacy Pub Date : 2020-10-17 DOI: 10.1145/3458903.3458905

Sandhya Koteshwara, M. Kumar, P. Pattnaik

引用次数: 0

Implementing the Draft RISC-V Scalar Cryptography Extensions 实现RISC-V标量加密扩展草案

Hardware and Architectural Support for Security and Privacy Pub Date : 2020-10-17 DOI: 10.1145/3458903.3458904

Ben Marshall, D. Page, T. Pham

引用次数: 2

Uncovering Hidden Instructions in Armv8-A Implementations 揭示Armv8-A实现中的隐藏指令

Hardware and Architectural Support for Security and Privacy Pub Date : 2020-10-17 DOI: 10.1145/3458903.3458906

Fredrik Strupe, Rakesh Kumar

{"title":"Uncovering Hidden Instructions in Armv8-A Implementations","authors":"Fredrik Strupe, Rakesh Kumar","doi":"10.1145/3458903.3458906","DOIUrl":"https://doi.org/10.1145/3458903.3458906","url":null,"abstract":"Though system and application level security has received and continue to receive significant attention, interest in hardware security has spiked only in the last few years. The majority of recently disclosed hardware security attacks exploit well known and documented hardware behaviours such as speculation, cache and memory timings, etc. We observe that security exploits in undocumented hardware behaviour can have even more severe consequences as such behaviour is rarely verified and protected against. This paper introduces armshaker, a tool to uncover one such undocumented behaviour in the Armv8 architecture, namely hidden instructions. These are the instructions that are not documented in the ISA reference manual, but still execute successfully. We tested five different Armv8-A hardware platforms from four different vendors, as well as two Armv8-A emulators, and uncovered multiple hidden instructions. An interesting finding is that, though we did not discover any hidden instruction in the hardware itself, bugs in the system software can induce hidden instructions in the system that, from a user’s perspective, are indistinguishable from hidden instructions in hardware. Though armshaker did not find any hidden instruction in the hardware of the tested platforms, their existence cannot be ruled out, given the diversity of available Arm processors. Consequently, we make armshaker publicly available as open-source software to enable users to audit their own systems for hidden instructions.","PeriodicalId":141766,"journal":{"name":"Hardware and Architectural Support for Security and Privacy","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122134096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

SoK: Opportunities for Software-Hardware-Security Codesign for Next Generation Secure Computing SoK:下一代安全计算的软硬件安全协同设计机会

Hardware and Architectural Support for Security and Privacy Pub Date : 2020-10-17 DOI: 10.1145/3458903.345891

Deeksha Dangwal, M. Cowan, Armin Alaghi, Vincent T. Lee, Brandon Reagen, Caroline Trippel

{"title":"SoK: Opportunities for Software-Hardware-Security Codesign for Next Generation Secure Computing","authors":"Deeksha Dangwal, M. Cowan, Armin Alaghi, Vincent T. Lee, Brandon Reagen, Caroline Trippel","doi":"10.1145/3458903.345891","DOIUrl":"https://doi.org/10.1145/3458903.345891","url":null,"abstract":"Users are demanding increased data security. As a result, security is rapidly becoming a first-order design constraint in next generation computing systems. Researchers and practitioners are exploring various security technologies to meet user demand such as trusted execution environments (e.g., Intel SGX, ARM TrustZone), homomorphic encryption, and differential privacy. Each technique provides some degree of security, but differs with respect to threat coverage, performance overheads, as well as implementation and deployment challenges. In this paper, we present a systemization of knowledge (SoK) on these design considerations and trade-offs using several prominent security technologies. Our study exposes the need for software-hardware-security codesign to realize efficient and effective solutions of securing user data. In particular, we explore how design considerations across applications, hardware, and security mechanisms must be combined to overcome fundamental limitations in current technologies so that we can minimize performance overhead while achieving sufficient threat model coverage. Finally, we propose a set of guidelines to facilitate putting these secure computing technologies into practice.","PeriodicalId":141766,"journal":{"name":"Hardware and Architectural Support for Security and Privacy","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128303089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Position Paper:Defending Direct Memory Access with CHERI Capabilities 立场文件:用CHERI功能保护直接内存访问

Hardware and Architectural Support for Security and Privacy Pub Date : 2020-10-17 DOI: 10.1145/3458903.3458910

A. T. Markettos, John Baldwin, Ruslan Bukin, P. Neumann, S. Moore, R. Watson

引用次数: 3

SIMD Instruction Set Extensions for Keccak with Applications to SHA-3, Keyak and Ketje SIMD指令集扩展为Keccak与应用程序到SHA-3, Keyak和Ketje

Hardware and Architectural Support for Security and Privacy Pub Date : 2016-06-18 DOI: 10.1145/2948618.2948622

Hemendra K. Rawat, P. Schaumont

{"title":"SIMD Instruction Set Extensions for Keccak with Applications to SHA-3, Keyak and Ketje","authors":"Hemendra K. Rawat, P. Schaumont","doi":"10.1145/2948618.2948622","DOIUrl":"https://doi.org/10.1145/2948618.2948622","url":null,"abstract":"Recent processor architectures such as Intel Westmere (and later) and ARMv8 include instruction-level support for the Advanced Encryption Standard (AES), for the Secure Hashing Standard (SHA-1, SHA2) and for carry-less multiplication. These crypto-instruction sets provide specialized hardware processing at the top of the memory hierarchy, and provide significant performance improvements over general-purpose software for common cryptographic operations. We propose a crypto-instruction set for the Keccak cryptographic sponge and for the Keccak duplex construction. Our design is integrated on a 128 bit SIMD interface, applicable to the ARM NEON and Intel AVX (128 bit) architecture. The proposed instruction set is optimized for flexibility and supports multiple variants of the Keccak-f[b] permutation, for b equal to 200, 400, 800, or 1600 bit. We investigate the performance of the design using the GEM5 micro-architecture simulator. Compared to the latest hand-optimized results, we demonstrate a performance improvement of 2 times (over NEON programming) to 6 times (over Assembly programming). For example, an optimized NEON implementation of SHA3-512 computes a hash at 48.1 instructions per byte, while our design uses 21.9 instructions per byte. The NEON optimized version of the Lake Keyak AEAD uses 13.4 instructions per byte, while our design uses 7.7 instructions per byte. We provide comprehensive performance evaluation for multiple configurations of the Keccak-f[b] permutation in multiple applications (Hash, Encryption, AEAD). We also analyze the hardware cost of the proposed instructions in gate-equivalent of 90nm standard cells, and show that the proposed instructions only require 4658 GE, a fraction of the cost of a full ARM Cortex-A9.","PeriodicalId":141766,"journal":{"name":"Hardware and Architectural Support for Security and Privacy","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134357469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Intel® Software Guard Extensions (Intel® SGX) Software Support for Dynamic Memory Allocation inside an Enclave Intel®Software Guard Extensions (Intel®SGX)软件支持Enclave内的动态内存分配

Hardware and Architectural Support for Security and Privacy Pub Date : 2016-06-18 DOI: 10.1145/2948618.2954330

Bin Cedric Xing, Mark Shanahan, Rebekah Leslie-Hurd

引用次数: 58

Using Scan Side Channel for Detecting IP Theft 利用扫描侧通道检测IP盗窃

Hardware and Architectural Support for Security and Privacy Pub Date : 2016-06-18 DOI: 10.1145/2948618.2948619

Leonid Azriel, R. Ginosar, S. Gueron, A. Mendelson

{"title":"Using Scan Side Channel for Detecting IP Theft","authors":"Leonid Azriel, R. Ginosar, S. Gueron, A. Mendelson","doi":"10.1145/2948618.2948619","DOIUrl":"https://doi.org/10.1145/2948618.2948619","url":null,"abstract":"We present a process for detection of IP theft in VLSI devices that exploits the internal test scan chains. The IP owner learns implementation details in the suspect device to find evidence of the theft, while the top level function is public. The scan chains supply direct access to the internal registers in the device, thus making it possible to learn the logic functions of the internal combinational logic chunks. Our work introduces an innovative way of applying Boolean function analysis techniques for learning digital circuits with the goal of IP theft detection. By using Boolean function learning methods, the learner creates a partial dependency graph of the internal flip-flops. The graph is further partitioned using the SNN graph clustering method, and individual blocks of combinational logic are isolated. These blocks can be matched with known building blocks that compose the original function. This enables reconstruction of the function implementation to the level of pipeline structure. The IP owner can compare the resulting structure with his own implementation to confirm or refute that an IP violation has occurred. We demonstrate the power of the presented approach with a test case of an open source Bitcoin SHA-256 accelerator, containing more than 80,000 registers. With the presented method we discover the microarchitecture of the module, locate all the main components of the SHA-256 algorithm, and learn the module's flow control.","PeriodicalId":141766,"journal":{"name":"Hardware and Architectural Support for Security and Privacy","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133754082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3