Hardware and Architectural Support for Security and Privacy最新文献_第3页

Security testing of a secure cache design

Hardware and Architectural Support for Security and Privacy Pub Date : 2013-06-23 DOI: 10.1145/2487726.2487729

Fangfei Liu, R. Lee

{"title":"Security testing of a secure cache design","authors":"Fangfei Liu, R. Lee","doi":"10.1145/2487726.2487729","DOIUrl":"https://doi.org/10.1145/2487726.2487729","url":null,"abstract":"Cache side channel attacks are attacks that leak secret information through physical implementation of cryptographic operations, nullifying cryptographic protection. Recently, these attacks have received great interest. Previous research found that software countermeasures alone are not enough to defend against cache side channel attacks. Secure cache designs can thwart the root causes of cache side channels and are more efficient. For instance, Newcache is a cache design that can enhance security, performance and power efficiency simultaneously through dynamic memory-cache remapping and eviction randomization. However, these cache designs seldom had their security verified experimentally by mounting cache side channel attacks on them.\u0000 In this paper, we test the security of Newcache using representative classes of cache side channel attacks proposed for conventional set-associative caches. The results show that Newcache can defeat all these attacks. However, what if a very knowledgeable attacker crafted the attack strategy targeting the secure caches design? We redesign the attacks specifically for Newcache. The results show that Newcache can defeat even crafted access-driven attacks specifically targeted at it but sometimes succumbs to the specifically crafted timing attacks, which is due to a very subtle vulnerability in its replacement algorithm. We further secure Newcache by modifying its replacement algorithm slightly, thus defeating these specifically crafted timing attacks. In addition, the improved Newcache simplifies the replacement algorithm in the original Newcache design.","PeriodicalId":141766,"journal":{"name":"Hardware and Architectural Support for Security and Privacy","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126610512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 30

Innovative instructions and software model for isolated execution 独立执行的创新指令和软件模型

Hardware and Architectural Support for Security and Privacy Pub Date : 2013-06-23 DOI: 10.1145/2487726.2488368

Francis X. McKeen, Ilya Alexandrovich, Alex Berenzon, Carlos V. Rozas, Hisham Shafi, Vedvyas Shanbhogue, U. Savagaonkar

引用次数: 1094

Unraveling timewarp: what all the fuzz is about? 解开时间隧道:所有的模糊是关于什么?

Hardware and Architectural Support for Security and Privacy Pub Date : 2013-06-23 DOI: 10.1145/2487726.2487734

Sarani Bhattacharya, C. Rebeiro, Debdeep Mukhopadhyay

引用次数: 6

Side channel vulnerability metrics: the promise and the pitfalls 侧通道漏洞度量:承诺和陷阱

Hardware and Architectural Support for Security and Privacy Pub Date : 2013-06-23 DOI: 10.1145/2487726.2487728

Tianwei Zhang, Fangfei Liu, Si Chen, R. Lee

引用次数: 37