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SLIM: a simulation and implementation language for VLSI microcode SLIM:一种用于VLSI微码的仿真和实现语言
ACM Sigmicro Newsletter Pub Date : 1985-05-01 DOI: 10.1145/1218048.1218050
J. Hennessy
{"title":"SLIM: a simulation and implementation language for VLSI microcode","authors":"J. Hennessy","doi":"10.1145/1218048.1218050","DOIUrl":"https://doi.org/10.1145/1218048.1218050","url":null,"abstract":"SLIM (Stanford Language for Implementing Microcode) is a programming language based system for specifying and simulating microcode in a VLSI chip. The language is oriented towards PLA implementations of microcoded machines using either a microprogram counter or a finite state machine. The SLIM system supports simulation of the microcode and will drive a PLA layout program to automatically create the PLA.","PeriodicalId":138968,"journal":{"name":"ACM Sigmicro Newsletter","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1985-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125115323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Review of "Advances in Microprogramming, by Efrem Mallach and Norman Sondak", Artech House Inc. 1983 《微程序设计的进展》，Efrem Mallach和Norman Sondak著，Artech House Inc.， 1983
ACM Sigmicro Newsletter Pub Date : 1984-09-01 DOI: 10.1145/1096464.1096469
W. Tracz
{"title":"Review of \"Advances in Microprogramming, by Efrem Mallach and Norman Sondak\", Artech House Inc. 1983","authors":"W. Tracz","doi":"10.1145/1096464.1096469","DOIUrl":"https://doi.org/10.1145/1096464.1096469","url":null,"abstract":"This book is an update of a previously published collection of papers on microprogramming titled \"Microprogramming\" (Artech House-1977). The editors have gathered together a sizeable collection (38) of articles related to the foundations of microprogramming, its fundamental principles, as well as the \"latest developments in the field of microprogramming\".","PeriodicalId":138968,"journal":{"name":"ACM Sigmicro Newsletter","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116966443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A source language performance monitoring facility for the B1800 Modula Interpreter B1800模块解释器的源语言性能监视工具
ACM Sigmicro Newsletter Pub Date : 1984-09-01 DOI: 10.1145/1096464.1096466
A. Hurst
{"title":"A source language performance monitoring facility for the B1800 Modula Interpreter","authors":"A. Hurst","doi":"10.1145/1096464.1096466","DOIUrl":"https://doi.org/10.1145/1096464.1096466","url":null,"abstract":"This note describes the features of a monitoring facility (called a software oscilloscope) installed on the Burroughs B1800 Modula Interpreter developed at ANU for use with the JAS operating system project [Hurst 83]. It allows dynamic monitoring of program behaviour at the source level, and provides a ready means for the evaluation of real time program behaviour.","PeriodicalId":138968,"journal":{"name":"ACM Sigmicro Newsletter","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127166367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
'Soft' computer speeds new system development “软”计算机加速了新系统的开发
ACM Sigmicro Newsletter Pub Date : 1984-09-01 DOI: 10.1145/1096464.1096467
John Aeberhard
{"title":"'Soft' computer speeds new system development","authors":"John Aeberhard","doi":"10.1145/1096464.1096467","DOIUrl":"https://doi.org/10.1145/1096464.1096467","url":null,"abstract":"PARIS, May 18 - An American computer system that's claimed to fill a 'special need in the computer industry' for an off-the-shelf machine that can mimic any digital architecture has found its first customer in Europe. Thomson Csf has installed the system, a QM-1 from Nanodata Computer Corporation of Buffalo, New York, at its Central Research Laboratory at Corbeville, Orsay, south of here.","PeriodicalId":138968,"journal":{"name":"ACM Sigmicro Newsletter","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115730679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Applying pipelining techniques to microprocessors 将流水线技术应用于微处理器
ACM Sigmicro Newsletter Pub Date : 1984-07-01 DOI: 10.1145/1096458.1096460
J. Slager, G. Louie, L. Gindraux, B. Rash
{"title":"Applying pipelining techniques to microprocessors","authors":"J. Slager, G. Louie, L. Gindraux, B. Rash","doi":"10.1145/1096458.1096460","DOIUrl":"https://doi.org/10.1145/1096458.1096460","url":null,"abstract":"Pipelining techniques are used in the Intel iAPX 286. High performance with full protection using normal speed memories require pipelining techniques. Pipelining gets the most done in each processor clock cycle. The internal pipelining is then exported to the memory bus to allow usage of slow memory devices.","PeriodicalId":138968,"journal":{"name":"ACM Sigmicro Newsletter","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125956113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Step-27 development station step27发展站
ACM Sigmicro Newsletter Pub Date : 1984-07-01 DOI: 10.1145/1096458.1096462
D. Wilburn, John R. Mick
{"title":"Step-27 development station","authors":"D. Wilburn, John R. Mick","doi":"10.1145/1096458.1096462","DOIUrl":"https://doi.org/10.1145/1096458.1096462","url":null,"abstract":"Step Engineering of Sunnyvale, California, has recently introduced the Step-27, a new Development Station that addresses the problems of the advanced microcoder. It offers the following features unavailable in other machines:• Internal RAM with ten-nanosecond access time; the fastest Writable Control Store (WCS) available,• In-line assembler/disassembler,• Real-time emulation of 29116 and 2910,• Sixteen-level state machine, and• Array sizes up to 512 bits wide by 65K deep in either single or multiple array configurations.","PeriodicalId":138968,"journal":{"name":"ACM Sigmicro Newsletter","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125679488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Microprocessor employs mainframe performance design techniques 微处理器采用大型机性能设计技术
ACM Sigmicro Newsletter Pub Date : 1984-07-01 DOI: 10.1145/1096458.1096459
J. Slager
{"title":"Microprocessor employs mainframe performance design techniques","authors":"J. Slager","doi":"10.1145/1096458.1096459","DOIUrl":"https://doi.org/10.1145/1096458.1096459","url":null,"abstract":"During the infancy of integrated circuit technology, designers still grappled with the problem of getting enough transistors on a reasonably sized die to enable them to design more than fundamental types of logic chips. Little more than a decade later, designers no longer are faced with that problem. On the contrary, with the hundred thousand and more transistors that can now be economically integrated, their task becomes one of deciding whether to add ancilliary functions on the same die as a microprocessor, or to use these transistors to embellish and speed up the microprocessor's activities.","PeriodicalId":138968,"journal":{"name":"ACM Sigmicro Newsletter","volume":"291 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121713641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
iAPX 286 microarchitecture to maximize performance iAPX 286微架构，以最大限度地提高性能
ACM Sigmicro Newsletter Pub Date : 1984-07-01 DOI: 10.1145/1096458.1096461
J. Slager, G. Louie, L. Gindraux
{"title":"iAPX 286 microarchitecture to maximize performance","authors":"J. Slager, G. Louie, L. Gindraux","doi":"10.1145/1096458.1096461","DOIUrl":"https://doi.org/10.1145/1096458.1096461","url":null,"abstract":"Designers of previous generations of microprocessors have relied heavily on ever higher clock frequencies in order to provide increased throughput. As successive generations of microprocessors become more and more optimized, it becomes necessary to increase the use of parallelism and pipelining in order to realize significant increases in throughput. The internal circuitry of the iAPX 286 is organized in such a way that throughput is significantly increased even though major functional enhancements, which would normally be expected to reduce throughput, are also implemented.","PeriodicalId":138968,"journal":{"name":"ACM Sigmicro Newsletter","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117351165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
LSI-CP: VLSI microprocessor emulates military processors LSI-CP: VLSI微处理器模拟军用处理器
ACM Sigmicro Newsletter Pub Date : 1984-03-01 DOI: 10.1145/1096453.1096456
Larry G. Zambotti, R. E. Hardy
{"title":"LSI-CP: VLSI microprocessor emulates military processors","authors":"Larry G. Zambotti, R. E. Hardy","doi":"10.1145/1096453.1096456","DOIUrl":"https://doi.org/10.1145/1096453.1096456","url":null,"abstract":"A Large Scale Integrated Central Processor (LSI-CP), see photo below, under development at IBM'S Federal System Division will address Department of Defense (DOD) standard computers. In particular, it executes the instructions sets of the AN/AYK-14 and AN/UYK-44 standard processors and will emulate other existing operational DOD computers.","PeriodicalId":138968,"journal":{"name":"ACM Sigmicro Newsletter","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128470392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Architecture quality 建筑质量
ACM Sigmicro Newsletter Pub Date : 1984-03-01 DOI: 10.1145/1096453.1096454
K. Kavi, K. Krishnamohan
{"title":"Architecture quality","authors":"K. Kavi, K. Krishnamohan","doi":"10.1145/1096453.1096454","DOIUrl":"https://doi.org/10.1145/1096453.1096454","url":null,"abstract":"During the past few years, researchers in Computer Architecture have seen a number of new, so called \"non- von Neumann\" innovations. Some of these innovations are finding their way into commercial computers, while others are relegated to the back waters of research logs. There are several reasons for the reluctance of manufacturers in implementing new ideas. One of the important reasons cited by the panel at NCC 81 [1] is the lack of quantitative data substantiating the benefits of the innovations. As one of the panelists remarked, \"we need an order of magnitude improvements, hopefully in base 10\", before new architectures can find their way into commercial computers.","PeriodicalId":138968,"journal":{"name":"ACM Sigmicro Newsletter","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133153637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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