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A tool for studying microprogramming 一个研究微程序设计的工具
ACM Sigmicro Newsletter Pub Date : 1984-03-01 DOI: 10.1145/1096453.1096455
Massimo Annunzjata, Walter Nosci, G. Sechi
{"title":"A tool for studying microprogramming","authors":"Massimo Annunzjata, Walter Nosci, G. Sechi","doi":"10.1145/1096453.1096455","DOIUrl":"https://doi.org/10.1145/1096453.1096455","url":null,"abstract":"The GIA (Applied Informatic Group) of IFC (Cosmic Physics Institute) of National Research Council has chosen microprogramming and 4-bit slices to design and build prototypal instruments.","PeriodicalId":138968,"journal":{"name":"ACM Sigmicro Newsletter","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124300526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
SRDAG compaction: a generalization of trace scheduling to increase the use of global context information SRDAG压缩:跟踪调度的泛化，以增加全局上下文信息的使用
ACM Sigmicro Newsletter Pub Date : 1983-12-01 DOI: 10.1145/1096419.1096423
J. Linn
{"title":"SRDAG compaction: a generalization of trace scheduling to increase the use of global context information","authors":"J. Linn","doi":"10.1145/1096419.1096423","DOIUrl":"https://doi.org/10.1145/1096419.1096423","url":null,"abstract":"Microcode compaction is the process of converting essentially vertical microcode into horizontal microcode for a given architecture. The conventional plan calls for a microcode compiler to generate vertical code for a given architecture and then use a compaction system to produce horizontal code, thereby greatly reducing the complexity of horizontal code generation.This paper attempts to extend the existing techniques used to perform the compaction process. Specifically, the procedure presented generalizes the \"trace scheduling\" method of [Fisher81] by using more global context information in compaction decisions. A number of definitions from classical compaction are generalized to encompass this expanded scope.Further, the paper presents two example classes of problem for which the new method outperforms the trace scheduling technique in terms of the execution time efficiency of the generated code. A number of unresolved questions are noted involving the class of global compaction procedures.","PeriodicalId":138968,"journal":{"name":"ACM Sigmicro Newsletter","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1983-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124891242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
Microprogrammed associative instructions: results and analysis of a case study in vertical migration 微程序关联指令:垂直迁移案例研究的结果和分析
ACM Sigmicro Newsletter Pub Date : 1983-12-01 DOI: 10.1145/1096419.1096437
B. Albert, A. Bode
{"title":"Microprogrammed associative instructions: results and analysis of a case study in vertical migration","authors":"B. Albert, A. Bode","doi":"10.1145/1096419.1096437","DOIUrl":"https://doi.org/10.1145/1096419.1096437","url":null,"abstract":"The microprogrammed implementation of associative instructions on conventional microprogrammable computers with address-based memory-access is introduced as \"vertical processing\". The implementation on the processors of the EGPA-multiprocessor project is reported as well as runtime comparisons of the microprograms with equivalent HLL-programs. The contribution of the factors vertical migration and associativity to the observed overall speedup is described. Finally, a detailed analysis of the underlying microarchitecture and the handcoded microprograms is given in view of local and global compaction techniques.","PeriodicalId":138968,"journal":{"name":"ACM Sigmicro Newsletter","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1983-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123806314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Toward type-oriented dynamic vertical migration 走向面向类型的动态垂直迁移
ACM Sigmicro Newsletter Pub Date : 1983-12-01 DOI: 10.1145/1096419.1096439
R. I. Winner, E. M. Carter
{"title":"Toward type-oriented dynamic vertical migration","authors":"R. I. Winner, E. M. Carter","doi":"10.1145/1096419.1096439","DOIUrl":"https://doi.org/10.1145/1096419.1096439","url":null,"abstract":"The study of structured programming has shown that through data abstraction, program reliability and maintainability can be improved. At the same time, vertical migration has been shown to be an effective way to improve the performance of programs. Contemporary techniques, however, tend to address the needs of only certain classes of programs and therefore may overlook or even preclude certain optimization opportunities. Dynamic microprogramming can overcome the problem of applicability of a particular vertical migration by allowing the migration to be tailored for each particular application. This paper describes a project which is exploring the interactions of these three concepts of dynamic microprogramming, vertical migration, and data abstraction and how they can be integrated to form a coherent facility which provides automated redefinition of computer architecture for each application model.","PeriodicalId":138968,"journal":{"name":"ACM Sigmicro Newsletter","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1983-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115166983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Improving the performance of UCSD Pascal via microprogramming on the PDP-11/60 在PDP-11/60上通过微编程提高UCSD Pascal的性能
ACM Sigmicro Newsletter Pub Date : 1983-12-01 DOI: 10.1145/1096419.1096440
Mark T. Schaefer, Y. Patt
{"title":"Improving the performance of UCSD Pascal via microprogramming on the PDP-11/60","authors":"Mark T. Schaefer, Y. Patt","doi":"10.1145/1096419.1096440","DOIUrl":"https://doi.org/10.1145/1096419.1096440","url":null,"abstract":"UCSD Pascal is implemented as a machine-independent virtual machine. This virtual machine is usually interpreted on a host computer by machine language instructions, which, in turn, are often interpreted by microcode. Performance of a virtual machine is generally a function of the number of levels of interpretation required to perform a computation. By bypassing one or more of these layers, it should be possible to enhance performance.To test this hypothesis, a Pascal interpreter was written for the PDP-11/60. After analysis of the Pascal machine, changes were made that interpreted selected portions of the virtual machine directly in microcode.This paper describes the microcode which was added, and discusses the improvements which resulted.","PeriodicalId":138968,"journal":{"name":"ACM Sigmicro Newsletter","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1983-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131410735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Axiomatic proof rules for a machine-specific microprogramming language 特定于机器的微程序设计语言的公理证明规则
ACM Sigmicro Newsletter Pub Date : 1983-12-01 DOI: 10.1145/1096419.1096442
Alan S. Wagner, S. Dasgupta
{"title":"Axiomatic proof rules for a machine-specific microprogramming language","authors":"Alan S. Wagner, S. Dasgupta","doi":"10.1145/1096419.1096442","DOIUrl":"https://doi.org/10.1145/1096419.1096442","url":null,"abstract":"In recent years, much effort has been devoted to the design and implementation of high level microprogramming languages. One of the goals for such languages is to facilitate the formal verification of microprograms using Hoare's inductive assertion method. Essential to the use of this method is an axiomatic definition of the microprogramming language.In this paper, we describe the axiomatization of the machine dependent microprogramming language S*(QM-1) [12]. This language is an instantiation of the machine independent language schema S* [3,4], for the Nanodata QM-1 \"nanolevel\" architecture. We show that, in spite of the complexity of the QM-1, with its variety of side-effects and special conditions, a small and uniform set of proof rules can be constructed.","PeriodicalId":138968,"journal":{"name":"ACM Sigmicro Newsletter","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1983-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131673627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
The logic engine development system support for microprogrammed bit-slice development 逻辑引擎开发系统支持微程序位片开发
ACM Sigmicro Newsletter Pub Date : 1983-12-01 DOI: 10.1145/1096419.1096433
F. Prosser, David E. Winkel
{"title":"The logic engine development system support for microprogrammed bit-slice development","authors":"F. Prosser, David E. Winkel","doi":"10.1145/1096419.1096433","DOIUrl":"https://doi.org/10.1145/1096419.1096433","url":null,"abstract":"The Logic Engine Development System is an integrated hardware and software system that aids the designer in many phases of microprogrammed bit-slice hardware design. It is the first commercially-available system to provide, direct support for the microprogram sequencer, or to supply a built-in host computer for the designer's use. The Logic Engine includes a new microassembler that encourages structured coding while remaining simple to use.Microprogramming permits the designer to tackle complex control tasks, but this ability to deal conceptually with complex designs brings with it numerous implementation problems. On what type of breadboard should we build the architecture? How will we debug the architecture? How will we produce the microcode? How will we load the microcode into a control store? How will we design and build the microinstruction sequencer? How will we debug the microcode? How will we modify the microcode?These questions imply that the designer will need a powerful support system to allow him to manage microprogrammed control. The control unit itself is only one part of a good development system. Such a system must provide support for the development and debugging of both the architecture and the control algorithm. The system should suppress the usual design headaches and subtleties of hardware construction. A development system should provide the convenience of wire-wrap for initial testing. It should provide lights and switches to assist the designer in displaying and controlling individual signals during the testing stages of design. Of course, it should give powerful support to the development, debugging, and modification of the control program.The Logic Engine Development System, manufactured by Logic Design, Inc., offers a high standard of performance for development systems for microprogrammed bit-slice design.","PeriodicalId":138968,"journal":{"name":"ACM Sigmicro Newsletter","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1983-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122263861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A design approach for a microprogrammed control unit with built in self test 一种内置自检的微程序控制单元的设计方法
ACM Sigmicro Newsletter Pub Date : 1983-12-01 DOI: 10.1145/1096419.1096428
Jordi Duran, T. Mangir
{"title":"A design approach for a microprogrammed control unit with built in self test","authors":"Jordi Duran, T. Mangir","doi":"10.1145/1096419.1096428","DOIUrl":"https://doi.org/10.1145/1096419.1096428","url":null,"abstract":"We present an architecture for concurrent testing of a microprogrammed control unit. This approach is compared with other control unit testing strategies. The advantages of this approach are: a) it allows testing of the control unit independent of the operational section, b) minimizes the hardcore, c) it is easily incorporated in microprogrammed control units, d) since it is concurrent, probability of detecting intertermittent errors is high, e) it is incorporated into the specification and therefore amenable for VLSI implementations.","PeriodicalId":138968,"journal":{"name":"ACM Sigmicro Newsletter","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1983-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133173527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Experimentation with a two-level microprogrammed multiprocessor computer 两级微程序多处理机实验
ACM Sigmicro Newsletter Pub Date : 1983-12-01 DOI: 10.1145/1096419.1096427
T. Baba, K. Yamazaki, Nobuyuki Hashimoto, H. Kanai, K. Okuda, Kazuhiko Hashimoto
{"title":"Experimentation with a two-level microprogrammed multiprocessor computer","authors":"T. Baba, K. Yamazaki, Nobuyuki Hashimoto, H. Kanai, K. Okuda, Kazuhiko Hashimoto","doi":"10.1145/1096419.1096427","DOIUrl":"https://doi.org/10.1145/1096419.1096427","url":null,"abstract":"MUNAP (MUlti-NAnoProgram machine) is a two-level microprogrammed multiprocessor computer designed and developed at a university as a research vehicle. This paper describes the experiences with the implementation of MUNAP. We start with a brief overview of the machine. We then describe the system organization both on hardware and support software. The architectural hierarchies defined on the basic hardware and software systems are described in detail. We conclude the paper with a list of the lessons we have learned from the experience.","PeriodicalId":138968,"journal":{"name":"ACM Sigmicro Newsletter","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1983-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127674804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
HLLDA defies RISC: thoughts on RISCs, CISCs, and HLLDAs HLLDA挑战RISC:关于RISC、CISCs和HLLDA的思考
ACM Sigmicro Newsletter Pub Date : 1983-12-01 DOI: 10.1145/1096419.1096430
W. C. Hopkins
{"title":"HLLDA defies RISC: thoughts on RISCs, CISCs, and HLLDAs","authors":"W. C. Hopkins","doi":"10.1145/1096419.1096430","DOIUrl":"https://doi.org/10.1145/1096419.1096430","url":null,"abstract":"High Level Language Directed Architectures (HLLDAs) are usually intended as ideal hosts for programs written in the supported languages. Patterson et al. [1] have claimed that, in general, a Complex Instruction Set Computer (CISC) is less efficient than a simpler computer with a sophisticated compiler. We claim in this note that HLLDAs should not all be lumped into this generalization, outline some HLLDA design criteria to avoid previously observed inefficiencies, and propose a unification strategy.","PeriodicalId":138968,"journal":{"name":"ACM Sigmicro Newsletter","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1983-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123056647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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