iAPX 286微架构,以最大限度地提高性能

J. Slager, G. Louie, L. Gindraux
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引用次数: 0

摘要

前几代微处理器的设计者在很大程度上依赖于更高的时钟频率,以提供更高的吞吐量。随着一代又一代的微处理器变得越来越优化,为了实现吞吐量的显著增加,有必要增加并行性和流水线的使用。iAPX 286的内部电路以这样一种方式组织,即使实现了通常预期会降低吞吐量的主要功能增强,也可以显着提高吞吐量。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
iAPX 286 microarchitecture to maximize performance
Designers of previous generations of microprocessors have relied heavily on ever higher clock frequencies in order to provide increased throughput. As successive generations of microprocessors become more and more optimized, it becomes necessary to increase the use of parallelism and pipelining in order to realize significant increases in throughput. The internal circuitry of the iAPX 286 is organized in such a way that throughput is significantly increased even though major functional enhancements, which would normally be expected to reduce throughput, are also implemented.
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