2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)最新文献_第6页

A conceptual toolchain for an application domain specific reconfigurable logic architecture 用于应用程序领域特定的可重构逻辑体系结构的概念性工具链

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032487

T. Bostelmann, S. Sawitzki

{"title":"A conceptual toolchain for an application domain specific reconfigurable logic architecture","authors":"T. Bostelmann, S. Sawitzki","doi":"10.1109/ReConFig.2014.7032487","DOIUrl":"https://doi.org/10.1109/ReConFig.2014.7032487","url":null,"abstract":"In this paper we present a concept of a reconfigurable logic toolchain. The specialty of this toolchain is the highly configurable architecture design. The goal is to provide the designer with the ability to suit the architecture of the reconfigurable logic to a specific application domain, for example communication or image processing. Thereby the disadvantages of very flexible, universal structures like FPGAs (inefficient resource usage and high communication overhead) can be diminished. At the same time their advantages (short time to market and low non-recurring engineering costs) can be kept. To achieve this a graphical architecture editor allows the user to adapt the global design structure as well as the detailed implementation of the logic cells. An analysis tool reports how frequently the different logic and routing resources of the described architecture are utilized by a given set of applications, to allow an optimization towards a specific application domain. We show the degrees of freedom the envisioned toolchain offers and discuss the corresponding trade-offs. Furthermore we show which steps of the development toolchain have to be adapted to the needs of such a flexible architecture and how this can be done. Finally we present the status of this work in progress and give a prospect to the planned future work.","PeriodicalId":137331,"journal":{"name":"2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)","volume":"44 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113999964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

FPGA-based design and implementation of direct torque control for induction machines 基于fpga的感应电机直接转矩控制的设计与实现

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032520

M. Zare, R. Kavasseri, Cristinel Ababei

引用次数: 8

Energy-efficient histogram on FPGA FPGA上的能效直方图

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032517

Andrea Sanny, Y. Yang, V. Prasanna

{"title":"Energy-efficient histogram on FPGA","authors":"Andrea Sanny, Y. Yang, V. Prasanna","doi":"10.1109/ReConFig.2014.7032517","DOIUrl":"https://doi.org/10.1109/ReConFig.2014.7032517","url":null,"abstract":"The construction of histograms is an integral part of image processing pipelines, useful for image editing features such as histogram matching, thresholding and histogram equalization. In the past, research done on kernels used in image processing pipelines target advancements to achieve high throughput, area efficiency and low cost. However, a growing topic of interest that has not been fully explored is the use of energy efficiency as a key metric. In this work, we focus on developing an energy-efficient histogram implementation with a minimum frame rate of at least 30 frames per second. We determine the components that consume the most power and propose an optimized histogram implementation with the utilization of multiple optimizations to achieve notable improvement in energy efficiency while maintaining suitable throughput for usage within image processing pipelines. These optimizations include a data-defined memory activation schedule, a careful data layout and circuit-level pipelining. Our architecture is implemented on commonly-used image sizes which vary from 240 × l28 to 1216×912 and assume a pixel width of 16 bits per pixel. The post place-and-route results show that our optimized architecture has up to 15.3× higher energy efficiency when compared against the baseline architecture.","PeriodicalId":137331,"journal":{"name":"2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121288063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

High-speed implementation of bcrypt password search using special-purpose hardware 使用专用硬件的bcrypt密码搜索的高速实现

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032529

Friedrich Wiemer, Ralf Zimmermann

引用次数: 22

Automatic cache partitioning and time-triggered scheduling for real-time MPSoCs 实时mpsoc的自动cache分区和时间触发调度

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032502

Gang Chen, Biao Hu, Kai Huang, A. Knoll, Kai Huang, Di Liu, T. Stefanov

{"title":"Automatic cache partitioning and time-triggered scheduling for real-time MPSoCs","authors":"Gang Chen, Biao Hu, Kai Huang, A. Knoll, Kai Huang, Di Liu, T. Stefanov","doi":"10.1109/ReConFig.2014.7032502","DOIUrl":"https://doi.org/10.1109/ReConFig.2014.7032502","url":null,"abstract":"Shared cache in modern multi-core systems has been considered as one of the major factors that degrade system predictability and performance. How to manage the shared cache for real-time multi-core systems in order to optimize the system performance while guaranteeing the system predictability is still an open issue. In this paper, we present a framework that can exploit cache management for real-time MPSoCs. The framework supports dynamic way-based cache partitioning at hardware level, building task-level time-triggered reconfigurable-cache MPSoCs. It automatically determines time-triggered schedule and cache configuration for each task to improve the system performance while guarantee the realtime constraints. We evaluate the proposed framework with respect to different numbers of cores and cache modules and prototype the constructed MPSoCs on FPGA. Experiment results based on FPGA implementation demonstrate the effectiveness of the proposed framework over the state-of-the-art cache management strategies when tested 27 benchmark programs on the constructed MPSoCs.","PeriodicalId":137331,"journal":{"name":"2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132843568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

An FPGA-based all-digital 802.11b & 802.15.4 receiver for the Software Defined Radio paradigm 基于fpga的全数字802.11b和802.15.4接收机，用于软件定义无线电范例

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032499

Alfredo Espinoza-Rhoton, L. F. Gonzalez-Perez, J. L. Ponce, B. Hector, Lennin C. Yllescas-Calderon, R. Parra-Michel, H. Aboushady

引用次数: 4

Phenox: Zynq 7000 based quadcopter robot Phenox:基于zynq7000的四轴飞行器机器人

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032546

Ryo Konomura, K. Hori

引用次数: 12

High-performance FPGA implementations of volterra DFEs for optical fiber systems 光纤系统volterra dfe的高性能FPGA实现

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032528

A. Emeretlis, G. Theodoridis, G. Glentis

引用次数: 7

Rotated parallel mapping: A novel approach for mapping data parallel applications on CGRAs 旋转并行映射:一种在CGRAs上映射数据并行应用程序的新方法

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032554

Simon Schulz, O. Bringmann, Thomas Schweizer, W. Rosenstiel

引用次数: 1

Hardware Task-Status Manager for an RTOS with FIFO communication 具有FIFO通信的RTOS硬件任务状态管理器

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) Pub Date : 2014-12-01 DOI: 10.1109/ReConFig.2014.7032527

P. Zaykov, G. Kuzmanov, A. Molnos, K. Goossens

{"title":"Hardware Task-Status Manager for an RTOS with FIFO communication","authors":"P. Zaykov, G. Kuzmanov, A. Molnos, K. Goossens","doi":"10.1109/ReConFig.2014.7032527","DOIUrl":"https://doi.org/10.1109/ReConFig.2014.7032527","url":null,"abstract":"In this paper, we address the problem of improving the performance of real-time embedded Multiprocessor System-on-Chip (MPSoC). Such MPSoCs often execute data-flow applications composed of multiple tasks, which communicate through First-In-First-Out (FIFO) queues. The tasks on each processor in the MPSoC are scheduled for execution by an instance of a Real-Time Operating System (RTOS). To improve performance, we propose a Hardware Task-Status Manager (HWTSM) block that reduces the Worst Case Execution Time (WCET) of the RTOS. The HWTSM is a Molen-style Custom Computing Unit (CCU), a coprocessor that determines the execution eligibility of tasks from FIFO-filling information. Furthermore, we propose a new processor-coprocessor execution model, denoted as parallel non-blocking. In this model the HWTSM execution overlaps with the execution of RTOS and user applications. The HWTSM is integrated into the existing CompSoC platform and this entire system is prototyped on a Xilinx XC5VFX130T FPGA chip. We experiment with two types of applications running in software, i.e., synthetic and real. With the synthetic applications, the results indicate a WCET reduction of the RTOS between 1.1 and 3.0 times. For each one of the real applications - JPEG and H.264 decoders, the experimental results indicate a WCET reduction of the RTOS by 1.3 and 1.6 times, respectively. The overall system performance gain vary from from 0.9% to 13.3% for synthetic applications, from 2.3% to 4.6% for the JPEG decoder, and from 3.8% to 7.5% for the H.264 decoder.","PeriodicalId":137331,"journal":{"name":"2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134016677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4