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2005 IEEE International Conference on Microelectronic Systems Education (MSE'05)最新文献

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Teaching formal methods within system-on-a-programmable-chip design 在可编程芯片系统设计中教授正式方法
2005 IEEE International Conference on Microelectronic Systems Education (MSE'05) Pub Date : 2005-06-12 DOI: 10.1109/MSE.2005.53
L. Gomes, Anikó Costa
{"title":"Teaching formal methods within system-on-a-programmable-chip design","authors":"L. Gomes, Anikó Costa","doi":"10.1109/MSE.2005.53","DOIUrl":"https://doi.org/10.1109/MSE.2005.53","url":null,"abstract":"The paper analyses the use of formal methods within a digital systems design process, having programmable logic devices as implementation devices. An alternative paper title could be \"From modeling formalisms to SoPC (system-on-a-programmable-chip) implementations on FPGAs\", where the emphasis is put on the design of the control/reactive part of the system. A set of formalisms have been considered for the task, ranging from state diagrams to Petri nets, and including state diagrams with data-paths, hierarchical and concurrent state diagrams, and statecharts. How to handle concurrency modeling through the referred set of formalisms is analyzed using a set of mini-projects, which are proposed as exercises to the students. Implementation platforms include FPGAs and CPLDs (complex programmable logic devices), which give adequate flexibility for exercising different implementation strategies, allowing laboratory prototyping.","PeriodicalId":136753,"journal":{"name":"2005 IEEE International Conference on Microelectronic Systems Education (MSE'05)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129416388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
ipPROCESS: using a process to teach IP-core development ipPROCESS:使用进程来教授ip核开发
2005 IEEE International Conference on Microelectronic Systems Education (MSE'05) Pub Date : 2005-06-12 DOI: 10.1109/MSE.2005.38
Marília Lima, Andre Aziz, D. Alves, Patricia Lira, V. Schwambach, E. Barros
{"title":"ipPROCESS: using a process to teach IP-core development","authors":"Marília Lima, Andre Aziz, D. Alves, Patricia Lira, V. Schwambach, E. Barros","doi":"10.1109/MSE.2005.38","DOIUrl":"https://doi.org/10.1109/MSE.2005.38","url":null,"abstract":"The reusing of intellectual property cores has been an alternative to the increasing gap between design productivity and chip complexity of emerging system-on-chip (SoC) designs. But the design of IP-cores has its own challenges like portability, reusability, standards interfaces, well-defined and useful documentation, easy integration and so on. All these characteristics together make the design of an IP-core a complex task and in this way teaching this discipline has became a new challenge for educators. In this paper we present an experience about how the utilization of a well-defined development process can be used to facilitate and speed-up student learning.","PeriodicalId":136753,"journal":{"name":"2005 IEEE International Conference on Microelectronic Systems Education (MSE'05)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128317678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Improving embedded systems education: laboratory enhancements using programmable systems on chip 改进嵌入式系统教育:使用芯片上可编程系统的实验室增强
2005 IEEE International Conference on Microelectronic Systems Education (MSE'05) Pub Date : 2005-06-12 DOI: 10.1109/MSE.2005.36
S. Merchant, G. D. Peterson, D. Bouldin
{"title":"Improving embedded systems education: laboratory enhancements using programmable systems on chip","authors":"S. Merchant, G. D. Peterson, D. Bouldin","doi":"10.1109/MSE.2005.36","DOIUrl":"https://doi.org/10.1109/MSE.2005.36","url":null,"abstract":"Programmable systems on chip provide powerful capabilities to designers, including reconfigurable logic as well as embedded processors. Such devices can enhance computer engineering education by exposing students to advanced technologies while streamlining the costs and time for laboratory preparation, maintenance, and pedagogy.","PeriodicalId":136753,"journal":{"name":"2005 IEEE International Conference on Microelectronic Systems Education (MSE'05)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134409929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Digital systems design with ASIC and FPGA: a novel course using CD/DVD and on-line formats 基于ASIC和FPGA的数字系统设计:一门使用CD/DVD和在线格式的新课程
2005 IEEE International Conference on Microelectronic Systems Education (MSE'05) Pub Date : 2005-06-12 DOI: 10.1109/MSE.2005.27
W. Burleson, Sheng Xu
{"title":"Digital systems design with ASIC and FPGA: a novel course using CD/DVD and on-line formats","authors":"W. Burleson, Sheng Xu","doi":"10.1109/MSE.2005.27","DOIUrl":"https://doi.org/10.1109/MSE.2005.27","url":null,"abstract":"A new course at the University of Massachusetts Amherst in digital systems design uses a novel approach of comparing ASIC and FPGA technologies, implementations, methodologies, CAD tools and trends. The course builds on basic courses in VLSI, HDL-based design and programmable logic but introduces the design of large-scale systems and the associated methodologies and tools. Recent advancements due to Moore's law have resulted in significant challenges in physical design, including interconnection, power consumption, reliability and verification. These challenges are explored at a fundamental level as well as solutions in modern CAD tools from Cadence, Synopsys, Xilinx and Altera. Both ASIC and FPGA solutions are explored and the economic, performance, power and flexibility tradeoffs are studied for each technology. The course was offered to undergraduates, graduates and engineers in industry through live, CD/DVD and on-line formats. The course is fully archived on CD/DVD and on the Web at: http://www.ecs.umass.edu/ece/vspgroup/burleson /courses/559/.","PeriodicalId":136753,"journal":{"name":"2005 IEEE International Conference on Microelectronic Systems Education (MSE'05)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115414813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
FPGA-based autonomous vehicle competitions in a capstone design course 顶点设计课程中基于fpga的自动驾驶汽车竞赛
2005 IEEE International Conference on Microelectronic Systems Education (MSE'05) Pub Date : 2005-06-12 DOI: 10.1109/MSE.2005.31
D. J. Jackson, K. Ricks
{"title":"FPGA-based autonomous vehicle competitions in a capstone design course","authors":"D. J. Jackson, K. Ricks","doi":"10.1109/MSE.2005.31","DOIUrl":"https://doi.org/10.1109/MSE.2005.31","url":null,"abstract":"Robotic vehicle designs and competitions often serve as the basis for undergraduate senior capstone design courses in electrical and computer engineering. Such competitions are well suited to senior level design as they require the design and integration of a number of components. Also, design competition specifications can easily be formulated that require significant design without imposing a particular solution on the student design team. This paper describes the goals, content and experiences of a one semester capstone design course in which students design, implement and test an FPGA-based robotic vehicle capable of performing a number of competition specific tasks.","PeriodicalId":136753,"journal":{"name":"2005 IEEE International Conference on Microelectronic Systems Education (MSE'05)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121306584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Teaching computer organization with HDLs: an incremental approach 用HDLs教授计算机组织:一种渐进的方法
2005 IEEE International Conference on Microelectronic Systems Education (MSE'05) Pub Date : 2005-06-12 DOI: 10.1109/MSE.2005.51
J. Nestor
{"title":"Teaching computer organization with HDLs: an incremental approach","authors":"J. Nestor","doi":"10.1109/MSE.2005.51","DOIUrl":"https://doi.org/10.1109/MSE.2005.51","url":null,"abstract":"This paper describes the use of Verilog HDL in a series of design projects for an undergraduate computer organization course. Students are given Verilog \"working models\" of pedagogical designs that can first be simulated to enhance initial learning and then extended and modified to develop more in-depth understanding. Projects include adder/ALU design and processor design using the single cycle, multicycle, and pipelined processor implementations presented in the popular Patterson and Hennessy text. This incremental approach allows students to focus on the underlying concepts of the course as they become more familiar with Verilog. The models and supporting project assignments are available online at http://foghorn.cadlab.lafayette.edu/ece313/.","PeriodicalId":136753,"journal":{"name":"2005 IEEE International Conference on Microelectronic Systems Education (MSE'05)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128436163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
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