International Conference on Compilers, Architecture, and Synthesis for Embedded Systems最新文献_第7页

Smartphone-based assistive technologies for the blind 基于智能手机的盲人辅助技术

International Conference on Compilers, Architecture, and Synthesis for Embedded Systems Pub Date : 2009-10-11 DOI: 10.1145/1629395.1629427

P. Narasimhan, R. Gandhi, Dan Rossi

引用次数: 28

CheckerCore: enhancing an FPGA soft core to capture worst-case execution times CheckerCore:增强FPGA软核以捕获最坏情况下的执行时间

International Conference on Compilers, Architecture, and Synthesis for Embedded Systems Pub Date : 2009-10-11 DOI: 10.1145/1629395.1629421

J. Ouyang, R. Raghavendra, Sibin Mohan, Zhang Tao, Yuan Xie, F. Mueller

{"title":"CheckerCore: enhancing an FPGA soft core to capture worst-case execution times","authors":"J. Ouyang, R. Raghavendra, Sibin Mohan, Zhang Tao, Yuan Xie, F. Mueller","doi":"10.1145/1629395.1629421","DOIUrl":"https://doi.org/10.1145/1629395.1629421","url":null,"abstract":"Embedded processors have become increasingly complex, resulting in variable execution behavior and reduced timing predictability. On such processors, safe timing specifications expressed as bounds on the worst-case execution time (WCET) are generally too loose due to conservative assumptions about complex architectural features, timing anomalies and programmatic complexities. Hence, exploiting the latest architectures may not be an option for embedded systems with hard real-time constraints where deadline misses cannot be tolerated.\u0000 This work addresses these shortcomings by contributing CheckerCore. CheckerCore is a mode-enhanced SPARC v8 soft core processor synthesized on an FPGA. During regular execution the core adheres to its original specifications. But when operating in a special time-checking configuration, CheckerCore executes programs irrespective of inputs and steers execution intentionally along selected control flow paths. Such execution allows systematic derivation of worst-case execution time (WCET) bounds. This paper presents the overall design and implementation of CheckerCore and also illustrates its use in deriving accurate WCET bounds for a set of embedded benchmarks. Overall, CheckerCore proposes a realistic processor core enhancement that encapsulate processor details without revealing them to users while supporting safe bounding of WCETs. To the best of our knowledge, this is the first contribution of a WCET-enhancing microarchitectural feature besides full processor encapsulations.","PeriodicalId":136293,"journal":{"name":"International Conference on Compilers, Architecture, and Synthesis for Embedded Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129936936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Tabu search-based synthesis of dynamically reconfigurable digital microfluidic biochips 基于禁忌搜索的动态可重构数字微流控生物芯片合成

International Conference on Compilers, Architecture, and Synthesis for Embedded Systems Pub Date : 2009-10-11 DOI: 10.1145/1629395.1629423

E. Maftei, P. Pop, J. Madsen

{"title":"Tabu search-based synthesis of dynamically reconfigurable digital microfluidic biochips","authors":"E. Maftei, P. Pop, J. Madsen","doi":"10.1145/1629395.1629423","DOIUrl":"https://doi.org/10.1145/1629395.1629423","url":null,"abstract":"Microfluidic biochips are replacing the conventional biochemical analyzers, and are able to integrate on-chip all the necessary functions for biochemical analysis. The \"digital\" microfluidic biochips are manipulating liquids not as a continuous flow, but as discrete droplets, and hence they are highly reconfigurable and scalable. A digital biochip is composed of a two-dimensional array of cells, together with reservoirs for storing the samples and reagents. Several adjacent cells are dynamically grouped to form a virtual device, on which operations are executed. During the execution of an operation, the virtual device can be reconfigured to occupy a different group of cells on the array. In this paper, we present a Tabu Search metaheuristic for the synthesis of digital microfluidic biochips, which, starting from a biochemical application and a given biochip architecture, determines the allocation, resource binding, scheduling and placement of the operations in the application. In our approach, we consider moving the modules during their operation, in order to improve the completion time of the biochemical application. The proposed heuristic has been evaluated using three real-life case studies and ten synthetic benchmarks.","PeriodicalId":136293,"journal":{"name":"International Conference on Compilers, Architecture, and Synthesis for Embedded Systems","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122523612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 52

Streaming FFT on REDEFINE-v2: an application-architecture design space exploration 基于REDEFINE-v2的流FFT:一种应用架构设计空间探索

International Conference on Compilers, Architecture, and Synthesis for Embedded Systems Pub Date : 2009-10-11 DOI: 10.1145/1629395.1629414

Alexander Fell, M. Alle, Keshavan Varadarajan, P. Biswas, Saptarsi Das, Jugantor Chetia, S. Nandy, R. Narayan

{"title":"Streaming FFT on REDEFINE-v2: an application-architecture design space exploration","authors":"Alexander Fell, M. Alle, Keshavan Varadarajan, P. Biswas, Saptarsi Das, Jugantor Chetia, S. Nandy, R. Narayan","doi":"10.1145/1629395.1629414","DOIUrl":"https://doi.org/10.1145/1629395.1629414","url":null,"abstract":"In this paper we explore an implementation of a high-throughput, streaming application on REDEFINE-v2, which is an enhancement of REDEFINE. REDEFINE is a polymorphic ASIC combining the flexibility of a programmable solution with the execution speed of an ASIC. In REDEFINE Compute Elements are arranged in an 8x8 grid connected via a Network on Chip (NoC) called RECONNECT, to realize the various macrofunctional blocks of an equivalent ASIC. For a 1024-FFT we carry out an application-architecture design space exploration by examining the various characterizations of Compute Elements in terms of the size of the instruction store. We further study the impact by using application specific, vectorized FUs. By setting up different partitions of the FFT algorithm for persistent execution on REDEFINE-v2, we derive the benefits of setting up pipelined execution for higher performance. The impact of the REDEFINE-v2 micro-architecture for any arbitrary N-point FFT (N > 4096) FFT is also analyzed. We report the various algorithm-architecture tradeoffs in terms of area and execution speed with that of an ASIC implementation. In addition we compare the performance gain with respect to a GPP.","PeriodicalId":136293,"journal":{"name":"International Conference on Compilers, Architecture, and Synthesis for Embedded Systems","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128431355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Exposing non-standard architectures to embedded software using compile-time virtualisation 使用编译时虚拟化将非标准架构暴露给嵌入式软件

International Conference on Compilers, Architecture, and Synthesis for Embedded Systems Pub Date : 2009-10-11 DOI: 10.1145/1629395.1629417

Ian Gray, N. Audsley

引用次数: 21

Fine-grained parallel application specific computing for RNA secondary structure prediction using SCFGS on FPGA 基于FPGA的SCFGS对RNA二级结构预测的细粒度并行计算

International Conference on Compilers, Architecture, and Synthesis for Embedded Systems Pub Date : 2009-10-11 DOI: 10.1145/1629395.1629412

Y. Dou, Fei Xia, Jingfei Jiang

{"title":"Fine-grained parallel application specific computing for RNA secondary structure prediction using SCFGS on FPGA","authors":"Y. Dou, Fei Xia, Jingfei Jiang","doi":"10.1145/1629395.1629412","DOIUrl":"https://doi.org/10.1145/1629395.1629412","url":null,"abstract":"In the field of RNA secondary structure prediction, the CYK (Coche-Younger-Kasami) algorithm is a most popular methods using SCFG (stochastic context-free grammars) model. However, general purpose parallel computers including SMP multiprocessors or cluster systems exhibit low parallel efficiency and they are too expensive to be used easily for many research institutes. FPGA chips provide a new approach to accelerate the CYK algorithm by exploiting fine-grained custom design. The CYK algorithm shows complicated data dependence, in which the dependence distance is variable, and the dependence direction is also across two dimensions. We propose a systolic array structure including one master PE and multiple slave PEs for fine grain hardware implementation on FPGA. We partition tasks by columns and assign tasks to PEs for load balance. We exploit data reuse schemes to reduce the need to load matrix from external memory. To our knowledge, our implementation with 16 PEs is the only FPGA accelerator implementing the complete CYK/inside algorithm. The experimental results show a factor of more than 14 speedup over the Infernal-0.55 software running on a PC platform with Pentium 4 2.66GHz CPU. The computational power of our platform with FPGA accelerator is comparable to a PC cluster consisting of 20 Intel-Xeon CPUs for RNA secondary structure prediction using SCFGs, but the hardware cost and power consumption is only about 15% and 10% of the latter respectively.","PeriodicalId":136293,"journal":{"name":"International Conference on Compilers, Architecture, and Synthesis for Embedded Systems","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114700491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Parallel, hardware-supported interrupt handling in an event-triggered real-time operating system 在事件触发的实时操作系统中并行的、硬件支持的中断处理

International Conference on Compilers, Architecture, and Synthesis for Embedded Systems Pub Date : 2009-10-11 DOI: 10.1145/1629395.1629419

F. Scheler, Wanja Hofer, Benjamin Oechslein, R. Pfister, Wolfgang Schröder-Preikschat, D. Lohmann

引用次数: 24

Hybrid multithreading for VLIW processors VLIW处理器的混合多线程

International Conference on Compilers, Architecture, and Synthesis for Embedded Systems Pub Date : 2009-10-11 DOI: 10.1145/1629395.1629403

Manoj Gupta, F. Sánchez, J. Llosa

{"title":"Hybrid multithreading for VLIW processors","authors":"Manoj Gupta, F. Sánchez, J. Llosa","doi":"10.1145/1629395.1629403","DOIUrl":"https://doi.org/10.1145/1629395.1629403","url":null,"abstract":"Several multithreading techniques have been proposed to reduce resource underutilization in Very Long Instruction Word (VLIW) processors. Simultaneous MultiThreading (SMT) is a popular technique that improves processor performance by issuing multiple instructions from different threads. In VLIW processors, SMT requires extra hardware to merge instructions from different threads. The complexity of this hardware increases substantially with the number of threads. On the other hand, techniques like Interleaved MultiThreading (IMT) do not need any merging hardware, and support a larger number of threads at reasonable cost. In this paper, we propose Hybrid MultiThreading (HMT), a technique that at each cycle merges instructions from only a subset of threads. HMT supports a reasonable number of threads with a low merging hardware cost. For instance, it is possible to support 8 hardware threads with a merging hardware for only 2 threads. The experimental results show that using HMT improves the multithreading performance significantly. Further, supporting 8 hardware threads with HMT but using a 4-thread merging hardware achieves a performance similar to merging 8 threads simultaneously with a significantly lower merging hardware cost.","PeriodicalId":136293,"journal":{"name":"International Conference on Compilers, Architecture, and Synthesis for Embedded Systems","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134620994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

III-V/Si integration: potential and outlook for integrated low power micro and nanosystems III-V/Si集成:集成低功耗微纳米系统的潜力与前景

International Conference on Compilers, Architecture, and Synthesis for Embedded Systems Pub Date : 2009-10-11 DOI: 10.1145/1629395.1629399

S. Yoon

{"title":"III-V/Si integration: potential and outlook for integrated low power micro and nanosystems","authors":"S. Yoon","doi":"10.1145/1629395.1629399","DOIUrl":"https://doi.org/10.1145/1629395.1629399","url":null,"abstract":"Integration of III-V compound semiconductors with silicon on a monolithic platform has been a long term vision for the semiconductor industry. In the past, this concept began as a simple notion that the best physical properties of III-V semiconductors and devices could be married with the characteristics of the silicon manufacturing processes. However in recent years, the renewed interest in such heterogeneous technology is fueled by the interest to create an integrated system in silicon to continue to miniaturize with enhanced performance. Although the challenges to monolithically integrate III-V semiconductors with silicon began primarily as a technical investigation of GaAs epitaxial growth on silicon substrates, higher level technical solutions must be provided in the context of manufacturing to bridge viable short, medium and long term applications. In this talk, I shall describe our focus in research in III-V/Si monolithic integration in the context of materials science challenges, suggesting possible solutions to heterogeneous substrate issues that allow for silicon process integration and manufacturing, as well as producing monolithic III-V/Si integrated devices that could be enablers for future high performance platforms. I shall summarize the talk by speculating on the nature of applications that can potentially drive the integrated devices into the marketplace.","PeriodicalId":136293,"journal":{"name":"International Conference on Compilers, Architecture, and Synthesis for Embedded Systems","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134290128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A case study of on-chip sensor network in multiprocessor system-on-chip 多处理器片上系统中片上传感器网络的实例研究

International Conference on Compilers, Architecture, and Synthesis for Embedded Systems Pub Date : 2009-10-11 DOI: 10.1145/1629395.1629430

Yu Wang, Jiang Xu, Shengxi Huang, Weichen Liu, Huazhong Yang

{"title":"A case study of on-chip sensor network in multiprocessor system-on-chip","authors":"Yu Wang, Jiang Xu, Shengxi Huang, Weichen Liu, Huazhong Yang","doi":"10.1145/1629395.1629430","DOIUrl":"https://doi.org/10.1145/1629395.1629430","url":null,"abstract":"Reducing feature sizes and power supply voltage allows integrating more processing units (PUs) on multiprocessor system-on-chip (MPSoC) to satisfy the increasing demands of applications. However, it also makes MPSoC more susceptible to various reliability threats, such as high temperature and power/ground (P/G) noise. As the scale and complexity of MPSoC continuously increase, monitoring and mitigating reliability threats at run time could offer better performance, scalability, and flexibility for MPSoC designs. In this paper, we propose a systematic approach, on-chip sensor network (SENoC), to collaboratively detect, report, and alleviate run-time threats in MPSoC. SENoC not only detects reliability threats and shares related information among PUs, but also plans and coordinates the reactions of related PUs in MPSoC. SENoC is used and explained in our case study to alleviate the impacts of simultaneous switching noise in MPSoC's P/G network during power gating. Based on the detailed noise behaviors under different scenarios derived by our circuit-level MPSoC P/G noise simulation and analysis platform, simulation results show that SENoC helps to achieve on average 26.12% performance improvement compared with the traditional stop-go method with 1.4% area overhead in an 8*8-core MPSoC in 45nm.","PeriodicalId":136293,"journal":{"name":"International Conference on Compilers, Architecture, and Synthesis for Embedded Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131131903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5