2021 IEEE International Conference on Networking, Architecture and Storage (NAS)最新文献_第2页

PowerPrep: A power management proposal for user-facing datacenter workloads PowerPrep:面向用户的数据中心工作负载的电源管理建议

2021 IEEE International Conference on Networking, Architecture and Storage (NAS) Pub Date : 2021-10-01 DOI: 10.1109/nas51552.2021.9605364

V. Govindaraj, Sumitha George, M. Kandemir, J. Sampson, N. Vijaykrishnan

引用次数: 0

Message from Program Chairs 节目主持人的信息

2021 IEEE International Conference on Networking, Architecture and Storage (NAS) Pub Date : 2021-10-01 DOI: 10.1109/nas51552.2021.9605416

引用次数: 0

MLPP: Exploring Transfer Learning and Model Distillation for Predicting Application Performance MLPP:应用程序性能预测的迁移学习和模型蒸馏探索

2021 IEEE International Conference on Networking, Architecture and Storage (NAS) Pub Date : 2021-10-01 DOI: 10.1109/nas51552.2021.9605431

J. Gunasekaran, Cyan Subhra Mishra

{"title":"MLPP: Exploring Transfer Learning and Model Distillation for Predicting Application Performance","authors":"J. Gunasekaran, Cyan Subhra Mishra","doi":"10.1109/nas51552.2021.9605431","DOIUrl":"https://doi.org/10.1109/nas51552.2021.9605431","url":null,"abstract":"Performance prediction for applications is quintessential towards detecting malicious hardware and software vulnerabilities. Typically application performance is predicted using the profiling data generated from hardware tools such as linux perf. By leveraging the data, prediction models, both machine learning (ML) based and non ML-based have been proposed. However a majority of these models suffer from either loss in prediction accuracy, very large model sizes, and/or lack of general applicability to different hardware types such as wearables, handhelds, desktops etc. To address the aforementioned inefficiencies, in this paper we proposed MLPP, a machine learning based performance prediction model which can accurately predict application performance, and at the same time be easily transferable to a wide both mobile and desktop hardware platforms by leveraging transfer learning technique. Furthermore, MLPP incorporates model distillation techniques to significantly reduce the model size. Through our extensive experimentation and evaluation we show that MLPP can achieve up to 92.5% prediction accuracy while reducing the model size by up to 3.5 ×.","PeriodicalId":135930,"journal":{"name":"2021 IEEE International Conference on Networking, Architecture and Storage (NAS)","volume":"147 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125482240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Leveraging Network Delay Variability to Improve QoE of Latency Critical Services 利用网络延迟可变性提高延迟关键服务的QoE

2021 IEEE International Conference on Networking, Architecture and Storage (NAS) Pub Date : 2021-10-01 DOI: 10.1109/nas51552.2021.9605367

S. Shukla, M. Farrens

{"title":"Leveraging Network Delay Variability to Improve QoE of Latency Critical Services","authors":"S. Shukla, M. Farrens","doi":"10.1109/nas51552.2021.9605367","DOIUrl":"https://doi.org/10.1109/nas51552.2021.9605367","url":null,"abstract":"Even as cloud providers offer strict guarantees on the intra-cloud delay of requests for Latency-Critical (LC) Services, a high external network delay can result in a large end-to-end delay, causing a low user Quality of Experience (QoE). Furthermore, due to the variability in the external network delay, there is a disconnect between the user’s QoE and the cloud guaranteed service level objective (SLO). Specifically, a request that meets the SLO, can have a high or low QoE depending on the external network delay. In this work we propose a usercentric End-to-end Service Level Objective (ESLO), an extension of the traditional cloud-centric SLO, that guarantees stricter bounds on end-to-end delay and thereby achieving a higher QoE. We show how the variability in the external network delay can be both addressed and leveraged to meet the ESLO and improve server utilization. We propose ESLO-aware extensions to the Kubernetes infrastructure, that uses information about the external network delay and its distribution - (a) to reduce the number of QoE-violating responses by using deadline-based scheduling at the service instances, and (b) to appropriately scale service instances with load. We implement the ESLO-aware framework on the NSF Chameleon cloud testbed and present experimental results demonstrating the benefit of the proposed paradigm.","PeriodicalId":135930,"journal":{"name":"2021 IEEE International Conference on Networking, Architecture and Storage (NAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131344750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A Comprehensive Empirical Study of File Systems on Optane Persistent Memory 文件系统对Optane Persistent Memory的综合实证研究

2021 IEEE International Conference on Networking, Architecture and Storage (NAS) Pub Date : 2021-10-01 DOI: 10.1109/nas51552.2021.9605448

Yang Yang, Qian Cao, Shengjue Wang

{"title":"A Comprehensive Empirical Study of File Systems on Optane Persistent Memory","authors":"Yang Yang, Qian Cao, Shengjue Wang","doi":"10.1109/nas51552.2021.9605448","DOIUrl":"https://doi.org/10.1109/nas51552.2021.9605448","url":null,"abstract":"Emerging byte-addressable Non-volatile memories (NVM) are promising techniques as memory-like storage. Researchers have developed many NVM-aware file systems to exploit the benefits of NVM. However, many early file systems are usually evaluated based on DRAM-based simulations or emulations. Their experimental results cannot present the actual behaviors upon real NVM devices, since the devices do not perform like slow DRAMs as expected. In this paper, we provide a comprehensive empirical study of NVM-aware file systems on the first commercially available byte-addressable NVM (i.e., the Intel Optane DC Persistent Memory Module (PMM)). We evaluate and analyze the performance of the kernel-level file systems (XFS-DAX, Ext4-DAX, PMFS, and NOVA) and the user-space file systems (Strata and Libnvmmio) on PMM with various synthetic and real-world benchmarks (FIO, Filebench, FXmark, Redis, etc.). We also employ different file system configurations and different PMM configurations to evaluate their performance impact. We believe that the experimental results and performance analysis will provide implications for the developers of various applications and storage systems to reap the full characteristics of NVMs.","PeriodicalId":135930,"journal":{"name":"2021 IEEE International Conference on Networking, Architecture and Storage (NAS)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124153555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Cached Mapping Table Prefetching for Random Reads in Solid-State Drives 固态硬盘随机读取的缓存映射表预取

2021 IEEE International Conference on Networking, Architecture and Storage (NAS) Pub Date : 2021-10-01 DOI: 10.1109/nas51552.2021.9605397

X. Ruan, Xunfei Jiang, Haiquan Chen

引用次数: 1

Towards Energy-Efficient and Real-Time Cloud Computing 迈向节能和实时云计算

2021 IEEE International Conference on Networking, Architecture and Storage (NAS) Pub Date : 2021-10-01 DOI: 10.1109/nas51552.2021.9605453

T. Tekreeti, T. Cao, Xiaopu Peng, T. Bhattacharya, Jianzhou Mao, X. Qin, Wei-Shinn Ku

引用次数: 0

Efficient NVM Crash Consistency by Mitigating Resource Contention 通过减少资源争用实现高效的NVM崩溃一致性

2021 IEEE International Conference on Networking, Architecture and Storage (NAS) Pub Date : 2021-10-01 DOI: 10.1109/nas51552.2021.9605429

Zhiyuan Lu, Jianhui Yue, Yifu Deng, Yifeng Zhu

{"title":"Efficient NVM Crash Consistency by Mitigating Resource Contention","authors":"Zhiyuan Lu, Jianhui Yue, Yifu Deng, Yifeng Zhu","doi":"10.1109/nas51552.2021.9605429","DOIUrl":"https://doi.org/10.1109/nas51552.2021.9605429","url":null,"abstract":"Logging is widely adopted to ensure crash consistency for Non-Volatile Memory (NVM) systems. However, the logging imposes significant performance overhead caused by the extra log operations and ordering constraints between the logging and in-place updates, degrading the system performance. There are some research efforts to reduce the logging overhead. Recently, LAD proposed that exploiting the non-volatility of Asynchronous DRAM Refresh (ADR) buffer can remove log operations for a transaction whose total amount of updated cachelines is smaller than the buffer capacity, ensuring crash consistency. However, on multi-core systems, concurrent transactions contend the scarce ADR buffer and frequently lead to the buffer overflow. Upon the buffer overflow, LAD resorts to logging operations for in-flight transactions, degrading the system performance. Our experiments show that LAD produces a significant number of log operations when multiple transactions run concurrently. To decrease log operations caused by LAD, this paper presents a new transaction execution scheme, called two-stage transaction execution(TSTE), which allows the write requests of a transaction to be in both the ADR buffer and the staging SRAM buffer. Our new scheme performs log operations for a transaction’s write requests in the SRAM buffer and executes in-place update operations for this transaction’s write requests in the ADR buffer. The introduced SRAM buffer can make the ADR buffer serve more update requests, reducing log operations.The evaluation results demonstrate that our proposed schemes can efficiently reduce log operations up to 39.29% and improve the transaction throughput up to 28.22%","PeriodicalId":135930,"journal":{"name":"2021 IEEE International Conference on Networking, Architecture and Storage (NAS)","volume":"39 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115021274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Egress Engineering over BGP Label Unicast in MPLS-based Networks 基于mpls网络的BGP标签单播出口工程

2021 IEEE International Conference on Networking, Architecture and Storage (NAS) Pub Date : 2021-10-01 DOI: 10.1109/nas51552.2021.9605412

Sundaram Tirunelveli Radhakrishnan, S. Mohanty

引用次数: 0

GPU-Assisted Memory Expansion gpu辅助内存扩展

2021 IEEE International Conference on Networking, Architecture and Storage (NAS) Pub Date : 2021-10-01 DOI: 10.1109/nas51552.2021.9605372

Pisacha Srinuan, Purushottam Sigdel, Xu Yuan, Lu Peng, Paul Darby, Christopher Aucoin, N. Tzeng

{"title":"GPU-Assisted Memory Expansion","authors":"Pisacha Srinuan, Purushottam Sigdel, Xu Yuan, Lu Peng, Paul Darby, Christopher Aucoin, N. Tzeng","doi":"10.1109/nas51552.2021.9605372","DOIUrl":"https://doi.org/10.1109/nas51552.2021.9605372","url":null,"abstract":"Recent graphic processing units (GPUs) often come with large on-board physical memory to accelerate diverse parallel program executions on big datasets with regular access patterns, including machine learning (ML) and data mining (DM). Such a GPU may underutilize its physical memory during lengthy ML model training or DM, making it possible to lend otherwise unused GPU memory to applications executed concurrently on the host machine. This work explores an effective approach that lets memory-intensive applications run on the host machine CPU with its memory expanded dynamically onto available GPU on-board DRAM, called GPU-assisted memory expansion (GAME). Targeting computer systems equipped with the recent GPUs, our GAME approach permits speedy executions on CPU with large memory footprints by harvesting unused GPU on-board memory on-demand for swapping, far surpassing competitive GPU executions. Implemented in user space, our GAME prototype lets GPU memory house swapped-out memory pages transparently, without code modifications for high usability and portability. The evaluation of NAS-NPB benchmark applications demonstrates that GAME expedites monotasking (or multitasking) executions considerably by up to 2.1× (or 3.1×), when memory footprints exceed the CPU DRAM size and an equipped GPU has unused VDRAM available for swapping use.","PeriodicalId":135930,"journal":{"name":"2021 IEEE International Conference on Networking, Architecture and Storage (NAS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121828247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0