2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)最新文献_第2页

High-Speed and Low-Noise Multichannel System for Broadband Coherent Raman Imaging 宽带相干拉曼成像的高速低噪声多通道系统

2020 18th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2020-06-01 DOI: 10.1109/newcas49341.2020.9159786

A. Ragni, G. Sciortino, M. Sampietro, G. Ferrari, A. Cadena, F. Vernuccio, G. Cerullo, D. Polli

引用次数: 2

A Switchable, Passively Tuneable 28 GHz to 39 GHz Upconversion Link for a 5G Repeater using a Broadside Coupler and Analog Predistortion in a 130 nm BiCMOS Technology 一种可切换的、被动可调谐的28 GHz至39 GHz上转换链路，用于在130 nm BiCMOS技术中使用宽带耦合器和模拟预失真的5G中继器

2020 18th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2020-06-01 DOI: 10.1109/newcas49341.2020.9159779

Julian Potschka, J. Zuber, Katharina Kolb, Tim Maiwald, M. Dietz, A. Hagelauer, K. Aufinger, R. Weigel

引用次数: 0

Improved $pi$-Delayed Harmonic Rejection N-Path Mixer for Low Power Consumption and Multistandard Receiver 用于低功耗和多标准接收机的改进$pi$-延迟谐波抑制n路混频器

2020 18th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2020-06-01 DOI: 10.1109/newcas49341.2020.9159792

A. A. Shakoush, E. Lauga-Larroze, F. Podevin, S. Ibrahim, L. Fesquet, S. Bourdel

引用次数: 0

OTA-Free MASH Two-Step Incremental ADC based on Noise Shaping SAR ADCs 基于噪声整形SAR ADC的无ota MASH两步增量ADC

2020 18th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2020-06-01 DOI: 10.1109/newcas49341.2020.9159802

Masoume Akbari, M. Honarparvar, Y. Savaria, M. Sawan

引用次数: 1

A Novel Event Based Image Sensor with spacial and temporal redundancy suppression 一种具有时空冗余抑制的基于事件的图像传感器

2020 18th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2020-06-01 DOI: 10.1109/NEWCAS49341.2020.9159847

Mohamed Akrarai, Nils Margotat, G. Sicard, L. Fesquet

引用次数: 3

Wireless Devices Identification with Light-Weight Convolutional Neural Network Operating on Quadrant IQ Transition Image 基于象限IQ过渡图像的轻量级卷积神经网络无线设备识别

2020 18th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2020-06-01 DOI: 10.1109/newcas49341.2020.9159777

Hiro Tamura, K. Yanagisawa, A. Shirane, K. Okada

引用次数: 4

Digital Interpolating Phase Modulator Implementation for Outphasing PA 数字内插相位调制器的失相PA实现

2020 18th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2020-06-01 DOI: 10.1109/newcas49341.2020.9159834

G. Franco, Dang-Kièn Germain Pham, P. Desgreys

{"title":"Digital Interpolating Phase Modulator Implementation for Outphasing PA","authors":"G. Franco, Dang-Kièn Germain Pham, P. Desgreys","doi":"10.1109/newcas49341.2020.9159834","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159834","url":null,"abstract":"Recent wireless architectures have increased requirements in terms of power consumption and linearity. These requirements concern specially the power amplifier (PA) responsible for driving the antenna. One architecture proposed for this role is the outphasing amplifier, which realizes linear amplification using non-linear components. To generate the waveforms required by the switched-mode outphasing architecture, the Digital Interpolating Phase Modulator (DIPM) was proposed recently. It works by reconstructing a constant amplitude RF signal using several DSP engines. However, the authors only describe an implementation with four signal processing engines by hypothesis. In this paper, an implementation of the DIPM algorithm is developed, alongside an exploration on the number of signal processing engines used. Furthermore, the digital design is synthesized in two different process technologies to contrast power and area utilization. Our simulations confirm their choice of number of engines if power is a constraint. However, other requirements, such as technology used, may lead to different solutions.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117074942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Quantized Guided Pruning for Efficient Hardware Implementations of Deep Neural Networks 深度神经网络高效硬件实现的量化导向剪枝

2020 18th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2020-06-01 DOI: 10.1109/newcas49341.2020.9159769

G. B. Hacene, Vincent Gripon, M. Arzel, Nicolas Farrugia, Y. Bengio

{"title":"Quantized Guided Pruning for Efficient Hardware Implementations of Deep Neural Networks","authors":"G. B. Hacene, Vincent Gripon, M. Arzel, Nicolas Farrugia, Y. Bengio","doi":"10.1109/newcas49341.2020.9159769","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159769","url":null,"abstract":"Deep Neural Networks (DNNs) in general and Convolutional Neural Networks (CNNs) in particular are state-of-the-art in numerous computer vision tasks such as object classification and detection. However, the large amount of parameters they contain leads to a high computational complexity and strongly limits their usability in budget-constrained devices such as embedded devices. In this paper, we propose a combination of a pruning technique and a quantization scheme that effectively reduce the complexity and memory usage of convolutional layers of CNNs, by replacing the complex convolutional operation by a low-cost multiplexer. We perform experiments on CIFAR10, CIFAR100 and SVHN datasets and show that the proposed method achieves almost state-of-the-art accuracy, while drastically reducing the computational and memory footprints compared to the baselines. We also propose an efficient hardware architecture, implemented on Field Programmable Gate Arrays (FPGAs), to accelerate inference, which works as a pipeline and accommodates multiple layers working at the same time to speed up the inference process. In contrast with most proposed approaches which have used external memory or software defined memory controllers, our work is based on algorithmic optimization and full-hardware design, enabling a direct, on-chip memory implementation of a DNN while keeping close to state of the art accuracy.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"8 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123082602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A Rigorous Analysis on Quadrature Single-Ended Ring Oscillators 正交单端环振子的严格分析

2020 18th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2020-06-01 DOI: 10.1109/newcas49341.2020.9159821

Saba Mohammadi, Michael M. Green

引用次数: 0

FlowTrojan: Insertion and Detection of Hardware Trojans on Flow-Based Microfluidic Biochips FlowTrojan:基于flow的微流控生物芯片上硬件木马的插入与检测

2020 18th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2020-06-01 DOI: 10.1109/NEWCAS49341.2020.9159820

Huili Chen, S. Potluri, F. Koushanfar

引用次数: 3