OTA-Free MASH Two-Step Incremental ADC based on Noise Shaping SAR ADCs

An OTA-free two-step incremental ADC (IADC) based on the noise-shaping successive approximation register (NS-SAR) topology is presented in this paper. During the first step, the ADC is configured as a multi-stage noise-shaping (MASH) 2–2 NS-SAR incremental ADC. During the second step, the first stage of the ADC is re-used to enhance the resolution of the incremental ADC. Employing 4-bit SAR ADCs as core quantizers, along with re-using parts of the hardware, can make this structure area and power-efficient. Simulation results, performed with MATLAB/SIMULINK, demonstrate the efficiency of the proposed ADC featuring a signal to quantization noise ratio (SQNR) of 150 dB, with an oversampling rate (OSR) of 48 over a 250 kHz bandwidth.