Masoume Akbari, M. Honarparvar, Y. Savaria, M. Sawan
{"title":"OTA-Free MASH Two-Step Incremental ADC based on Noise Shaping SAR ADCs","authors":"Masoume Akbari, M. Honarparvar, Y. Savaria, M. Sawan","doi":"10.1109/newcas49341.2020.9159802","DOIUrl":null,"url":null,"abstract":"An OTA-free two-step incremental ADC (IADC) based on the noise-shaping successive approximation register (NS-SAR) topology is presented in this paper. During the first step, the ADC is configured as a multi-stage noise-shaping (MASH) 2–2 NS-SAR incremental ADC. During the second step, the first stage of the ADC is re-used to enhance the resolution of the incremental ADC. Employing 4-bit SAR ADCs as core quantizers, along with re-using parts of the hardware, can make this structure area and power-efficient. Simulation results, performed with MATLAB/SIMULINK, demonstrate the efficiency of the proposed ADC featuring a signal to quantization noise ratio (SQNR) of 150 dB, with an oversampling rate (OSR) of 48 over a 250 kHz bandwidth.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/newcas49341.2020.9159802","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
An OTA-free two-step incremental ADC (IADC) based on the noise-shaping successive approximation register (NS-SAR) topology is presented in this paper. During the first step, the ADC is configured as a multi-stage noise-shaping (MASH) 2–2 NS-SAR incremental ADC. During the second step, the first stage of the ADC is re-used to enhance the resolution of the incremental ADC. Employing 4-bit SAR ADCs as core quantizers, along with re-using parts of the hardware, can make this structure area and power-efficient. Simulation results, performed with MATLAB/SIMULINK, demonstrate the efficiency of the proposed ADC featuring a signal to quantization noise ratio (SQNR) of 150 dB, with an oversampling rate (OSR) of 48 over a 250 kHz bandwidth.