IEEE Transactions on Software Engineering最新文献_第10页

TCRCA: Topology-Guided Causal Inference for Root Cause Analysis in Microservices TCRCA：微服务中根本原因分析的拓扑引导因果推理

IF 7.4 1区计算机科学

IEEE Transactions on Software Engineering Pub Date : 2026-07-21 DOI: 10.1109/tse.2026.3715410

Junjun Li, Shi Ying

引用次数: 0

Generalization or Memorization: Data Contamination for Large Language Models in Code Generation 泛化或记忆：代码生成中大型语言模型的数据污染

IF 7.4 1区计算机科学

IEEE Transactions on Software Engineering Pub Date : 2026-07-17 DOI: 10.1109/tse.2026.3713834

Yihong Dong, Xue Jiang, Xuanming Zhang, Huanyu Liu, Zhi Jin, Bin Gu, Mengfei Yang, Ge Li

引用次数: 0

Semantic Consensus Decoding: Backdoor Defense for Verilog Code Generation 语义一致解码：Verilog代码生成的后门防御

IF 7.4 1区计算机科学

IEEE Transactions on Software Engineering Pub Date : 2026-07-15 DOI: 10.1109/tse.2026.3713510

Guang Yang, Xing Hu, Xiang Chen, Xin Xia

引用次数: 0

Investigating Causality in Software Repositories Using Cohort-Based Methods 使用基于队列的方法调查软件存储库中的因果关系

IF 7.4 1区计算机科学

IEEE Transactions on Software Engineering Pub Date : 2026-07-15 DOI: 10.1109/tse.2026.3713676

Sira Vegas, Sabato Nocera, Giuseppe Scanniello, Natalia Juristo

引用次数: 0

Experience-Driven Test Case Generation for Deterministic MPI Programs 确定性MPI程序的经验驱动测试用例生成

IF 7.4 1区计算机科学

IEEE Transactions on Software Engineering Pub Date : 2026-07-08 DOI: 10.1109/tse.2026.3711752

Xiaoqi Zhao, Shuo Sun, Gai-Ge Wang, Dongyue Gao, Dunwei Gong

引用次数: 0

Understanding and Detecting Scalability Faults in Large-Scale Distributed Systems 大规模分布式系统中可扩展性故障的理解与检测

IF 7.4 1区计算机科学

IEEE Transactions on Software Engineering Pub Date : 2026-07-07 DOI: 10.1109/tse.2026.3710096

Hao-Nan Zhu, Goodness Ayinmode, Cesar A. Stuardo, Haryadi S. Gunawi, Cindy Rubio–González

引用次数: 0

Parameter-Efficient Fine-Tuning With Attributed Patch Semantic Graph for Automated Patch Correctness Assessment 基于属性补丁语义图的参数高效微调用于补丁正确性自动评估

IF 6 1区计算机科学

IEEE Transactions on Software Engineering Pub Date : 2026-07-01 Epub Date: 2026-04-14 DOI: 10.1109/TSE.2026.3684016

Zhenyu Yang;Jingwen Wu;Zhen Yang;Zhongxing Yu

{"title":"Parameter-Efficient Fine-Tuning With Attributed Patch Semantic Graph for Automated Patch Correctness Assessment","authors":"Zhenyu Yang;Jingwen Wu;Zhen Yang;Zhongxing Yu","doi":"10.1109/TSE.2026.3684016","DOIUrl":"10.1109/TSE.2026.3684016","url":null,"abstract":"Automated program repair (APR) aims to automatically repair program errors without human intervention, and recent years have witnessed a growing interest on this research topic. While much progress has been made and techniques originating from different disciplines have been proposed, APR techniques generally suffer from the patch overfitting issue, i.e., the generated patches are not genuinely correct despite they pass the employed tests. To alleviate this issue, many research efforts have been devoted for automated patch correctness assessment (APCA). In particular, with the emergence of large language model (LLM) technology, researchers have employed LLM to assess the patch correctness and have obtained the state-of-the-art performance. The literature on APCA has demonstrated the importance of capturing patch semantic and explicitly considering certain code attributes in predicting patch correctness. However, existing LLM-based methods typically treat code as token sequences and ignore the inherent formal structure for code, making it difficult to capture the deep patch semantics. Moreover, these LLM-based methods also do not explicitly account for enough code attributes. To overcome these drawbacks, we in this paper design a novel patch graph representation named attributed patch semantic graph (APSG), which adequately captures the patch semantic and explicitly reflects important patch attributes. To effectively use graph information in APSG, we accordingly propose a new parameter-efficient fine-tuning (PEFT) method of LLMs named Graph-LoRA. Our method focuses on the typical real-world scenarios where ground-truth patches are inaccessible, and does not rely on ground-truth patches to work. Extensive evaluations have been conducted to evaluate our method, and the results show that compared to the state-of-the-art methods, our method improves the accuracy and F1 score by 3.1% to 7.5% and 3.0% to 7.1% respectively.","PeriodicalId":13324,"journal":{"name":"IEEE Transactions on Software Engineering","volume":"52 7","pages":"1960-1979"},"PeriodicalIF":6.0,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147684758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Hetrify+: Improving the Verification Efficiency of RISC-V Heterogeneous Programs via Memory Access Specialization hetriify +：通过内存访问专门化提高RISC-V异构程序的验证效率

IF 6 1区计算机科学

IEEE Transactions on Software Engineering Pub Date : 2026-07-01 Epub Date: 2026-03-12 DOI: 10.1109/TSE.2026.3692469

Yiwei Li;Jiaxin Liu;Liangze Yin;Wei Dong;Shanshan Li;Jin Zhang

{"title":"Hetrify+: Improving the Verification Efficiency of RISC-V Heterogeneous Programs via Memory Access Specialization","authors":"Yiwei Li;Jiaxin Liu;Liangze Yin;Wei Dong;Shanshan Li;Jin Zhang","doi":"10.1109/TSE.2026.3692469","DOIUrl":"10.1109/TSE.2026.3692469","url":null,"abstract":"Heterogeneous software systems, which often combine closed-source libraries with exported interfaces, embedded assembly, and components in multiple languages, present significant challenges for formal verification. Our prior work, Hetrify, addressed this by converting RISC-V binaries into semantically equivalent C code, making such programs amenable to verification. However, its unified memory model required frequent dynamic computation of stack addresses, which significantly increased the size of the generated logical formulas, along with high memory usage and longer verification times. To address this, we propose memory access specialization, a static analysis and transformation technique that recovers fixed stack offsets during binary conversion to reduce verification overhead. By replacing symbolic stack accesses with fixed-offset memory references, it eliminates dynamic pointer arithmetic and reduces symbolic encoding complexity. This technique is integrated into Hetrify+, an enhanced verification tool for heterogeneous programs. To validate the effectiveness of our approach, we conduct both formal analysis and extensive empirical evaluation. Formal analysis guarantees the correctness of our method. In our evaluation, Hetrify+ demonstrates the same verification accuracy as the original Hetrify on 100 low-level RISC-V assembly programs, achieving up to 2.5<inline-formula><tex-math>$boldsymbol{times}$</tex-math></inline-formula> speedup and 4.9<inline-formula><tex-math>$boldsymbol{times}$</tex-math></inline-formula> reduction in memory usage. For 30 large-scale heterogeneous programs that include binary-only components, Hetrify+ maintains a 100% success rate, reducing verification time by 1.9<inline-formula><tex-math>$boldsymbol{times}$</tex-math></inline-formula> and memory consumption by 1.2<inline-formula><tex-math>$boldsymbol{times}$</tex-math></inline-formula>. These results demonstrate that memory access specialization is key to scaling the verification of heterogeneous programs.","PeriodicalId":13324,"journal":{"name":"IEEE Transactions on Software Engineering","volume":"52 7","pages":"2148-2172"},"PeriodicalIF":6.0,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148291607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Toward Understanding Functional Bugs in EVM-Based Blockchain Systems 了解基于evm的区块链系统中的功能缺陷

IF 6 1区计算机科学

IEEE Transactions on Software Engineering Pub Date : 2026-07-01 Epub Date: 2026-04-20 DOI: 10.1109/TSE.2026.3685454

Mingxi Ye;Yuhong Nan;Jianzhong Su;Zhijie Zhong;Yuming Xiao;Peilin Zheng;Zibin Zheng

{"title":"Toward Understanding Functional Bugs in EVM-Based Blockchain Systems","authors":"Mingxi Ye;Yuhong Nan;Jianzhong Su;Zhijie Zhong;Yuming Xiao;Peilin Zheng;Zibin Zheng","doi":"10.1109/TSE.2026.3685454","DOIUrl":"10.1109/TSE.2026.3685454","url":null,"abstract":"Functional bugs within blockchain systems have led to financial losses exceeding millions of dollars. Blockchain systems, such as Ethereum, play a critical role in supporting decentralized applications and managing significant financial assets. Despite the urgent need for enhanced security, relatively few studies have systematically investigated the functional bugs specific to blockchain systems. Unlike in conventional software, functional bugs in blockchain systems are often domain-specific and linked to core blockchain functionalities, necessitating a comprehensive understanding. In this study, we conduct a systematic analysis of functional bugs in Ethereum Virtual Machine (EVM)-based blockchain systems. We focus on the EVM-based architecture, as it is one of the most widely adopted models for blockchain systems. Specifically, we analyze bug-related issues reported in the GitHub repositories of leading blockchain systems, building a dataset of 205 real-world bugs classified into 18 categories. We investigate these collected bugs with respect to their taxonomies, root causes, and detection methods. From this analysis, we summarize eight key findings for enhancing blockchain security. The discovery of seven previously unknown bugs, yielding approximately $12,000 in bug bounties, demonstrates the practical impact of this work. A further investigation of state-of-the-art tools highlights the limitations of existing detection and analysis research.","PeriodicalId":13324,"journal":{"name":"IEEE Transactions on Software Engineering","volume":"52 7","pages":"2219-2232"},"PeriodicalIF":6.0,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147725611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Synthesis With Guided Environments 与引导环境的合成

IF 6 1区计算机科学

IEEE Transactions on Software Engineering Pub Date : 2026-07-01 Epub Date: 2026-04-22 DOI: 10.1109/TSE.2026.3686926

Orna Kupferman;Ofer Leshkowitz

{"title":"Synthesis With Guided Environments","authors":"Orna Kupferman;Ofer Leshkowitz","doi":"10.1109/TSE.2026.3686926","DOIUrl":"10.1109/TSE.2026.3686926","url":null,"abstract":"In the synthesis problem, we are given a specification, and we automatically generate a system that satisfies the specification in all environments. We introduce and study <italic>synthesis with guided environments</i> (SGE, for short), where the system may harness the knowledge and computational power of the environment during the interaction. The underlying idea in SGE is that in many real-life applications, in particular when the system serves or directs the environment, it is in the environment’s interest that the specification is satisfied; hence, it is reasonable to consider satisfaction of the specification only in environments that follow the system’s guidance. Thus, while the environment is still hostile, in the sense that the system should satisfy the specification no matter how the environment assigns values to the input signals, in SGE the system assigns values to some output signals and guides the environment via <italic>programs</i> how to assign values to other output signals. A key issue is that these assignments may depend on input signals that are hidden from the system but are known to the environment. SGE is thus particularly useful in settings where the system has partial visibility. In software systems, this corresponds to settings that involve hidden user intents, client-local states, or private service policies. We solve the problem of SGE, show its superiority with respect to traditional synthesis, and study theoretical aspects of SGE, like the complexity (memory and domain) of programs used by the system, SGE for branching-time specifications, and the connection of SGE to synthesis of (possibly distributed) systems with partial visibility.","PeriodicalId":13324,"journal":{"name":"IEEE Transactions on Software Engineering","volume":"52 7","pages":"2013-2030"},"PeriodicalIF":6.0,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11493573","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147735979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0