{"title":"Dynamic energy and reliability management in network-on-chip based chip multiprocessors","authors":"M. Moghaddam","doi":"10.1109/IGCC.2017.8323594","DOIUrl":"https://doi.org/10.1109/IGCC.2017.8323594","url":null,"abstract":"I investigate techniques for dynamic reliability management (DRM) and dynamic energy management (DEM) in future network-on-chip based chip multiprocessors (CMPs). I propose and study a hybrid dynamic lifetime reliability management algorithm that combines thread migration and dynamic voltage and frequency scaling (DVFS) techniques so that lifetime reliability of the overall system is increased to the desired target with minimal performance degradation. Furthermore, I introduce a novel algorithm for dynamic energy management under performance constraints. The proposed algorithm is a very effective heuristic that also uses the DVFS technique and a very efficient workload prediction technique based on Kalman filtering and long-short-term-memory (LSTM). In addition, this work is going to take advantage of deep neural networks (DNN) models in the next phase of this dissertation.","PeriodicalId":133239,"journal":{"name":"2017 Eighth International Green and Sustainable Computing Conference (IGSC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131159817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Holistic energy efficient crosstalk mitigation in DRAM","authors":"A. Jones, R. Melhem, Donald Kline","doi":"10.1109/IGCC.2017.8323590","DOIUrl":"https://doi.org/10.1109/IGCC.2017.8323590","url":null,"abstract":"The scaling of DRAM to increasingly small geometries has resulted in considerable challenges to both reliability and energy consumption of memory systems. For example, this aggressive scaling has resulted in increased vulnerability to both bitline and wordline crosstalk. Moreover, deep scaling has also introduced an understudied implication of dramatically increased embodied energy, or energy due to manufacturing memory integrated circuits. While many correction schemes have been proposed targeting, often independently, metrics of reliability and operational energy, recent studies have demonstrated that the impacts of manufacturing on reliability and holistic energy consumption must also be considered. In this work, we propose a technique to evaluate memory systems and their tradeoffs for reliability, embodied energy, and operational energy. We use this technique to examine several proposed correction schemes for DRAM faults. Further, we study a novel bitline crosstalk error correction scheme, Periodic Flip Encoding, which has considerable advantages in sustainability and reliability at high error rates.","PeriodicalId":133239,"journal":{"name":"2017 Eighth International Green and Sustainable Computing Conference (IGSC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115884956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hosein Mohammadi Makrani, Shahab Tabatabaei, S. Rafatirad, H. Homayoun
{"title":"Understanding the role of memory subsystem on performance and energy-efficiency of Hadoop applications","authors":"Hosein Mohammadi Makrani, Shahab Tabatabaei, S. Rafatirad, H. Homayoun","doi":"10.1109/IGCC.2017.8323591","DOIUrl":"https://doi.org/10.1109/IGCC.2017.8323591","url":null,"abstract":"The memory subsystem has always been one of the performance bottlenecks in computer systems. Given the large size of data, therefore, the questions of whether Big Data requires big memory and whether main memory subsystem plays an intrinsic role in the performance and energy-efficiency of Big Data are becoming important. In this paper, through a comprehensive real-system experimental analysis of performance, power and resource utilization, we have evaluated main memory characteristic of Hadoop MapReduce, a de facto standard for big data analytics. Through a methodical experimental setup we have analyzed the impact of DRAM capacity, operating frequency, and the number of channels on power and performance to understand the main memory requirements of this important Big Data framework. The characterization results across various Hadoop MapReduce applications from different domains illustrate that Hadoop MapReduce workloads show two distinct behaviors of being either CPU-intensive or Disk-intensive. Our experimental results showed that DRAM frequency as well as number of channels do not play a significant role on the performance of Hadoop workloads. On the other hand, our results indicate that increasing the number of DRAM channels reduces DRAM power and improves the energy-efficiency of Hadoop MapReduce applications.","PeriodicalId":133239,"journal":{"name":"2017 Eighth International Green and Sustainable Computing Conference (IGSC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125757444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Sustainable fault management and error correction for next-generation main memories","authors":"Donald Kline, R. Melhem, A. Jones","doi":"10.1109/IGCC.2017.8323584","DOIUrl":"https://doi.org/10.1109/IGCC.2017.8323584","url":null,"abstract":"As technology nodes continue to scale, main memories experience both increasing energy consumption as well as reliability challenges. In order to address rising failure rates due to problems with yield and runtime effects, such as crosstalk, due to process variation in small feature sizes, improved correction capabilities at the bit-level are increasingly essential. To address this challenge, we propose a sustainable approach to error correction in deeply scaled memories. In particular, we propose a novel area-efficient and sustainable fault map (SFaultMap) which targets holistic energy considerations to improve reliability while minimizing both operational and embodied energy. To demonstrate the effectiveness of SFaultMap we conduct a sustain-ability study, based on holistic energy consumption, to evaluate under which scenarios different solutions should be employed. In all cases and scenarios with moderate to high fault rates, SFaultMap has reduced energy over Error Correcting Pointers (ECP) for a five year lifetime. Moreover, as fault rate increases, the indifference time for ECP to recover upfront manufacturing energy increases from years to decades.","PeriodicalId":133239,"journal":{"name":"2017 Eighth International Green and Sustainable Computing Conference (IGSC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123032836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Understanding the impact of object oriented programming and design patterns on energy efficiency","authors":"Sepideh Maleki, Cuijiao Fu, Arun Banotra, Ziliang Zong","doi":"10.1109/IGCC.2017.8323605","DOIUrl":"https://doi.org/10.1109/IGCC.2017.8323605","url":null,"abstract":"With billions of lines of code being deployed and running on cloud servers, PCs, as well as battery-driven mobile phones, embedded systems, and IoT devices, software energy efficiency will play an increasingly important role in green IT. In the past decades, object oriented programming (OOP) has become the de facto standard for commercial software design. However, very little is known about the impact of OOP and design patterns on software energy efficiency. In this paper, we conduct an empirical study on a series of OOP features and design patterns and find out that their influences on performance and energy efficiency vary greatly. Some of them have negligible impact while others could degrade performance and increase energy consumption. If used appropriately, design patterns can also help improve performance and reduce energy consumption.","PeriodicalId":133239,"journal":{"name":"2017 Eighth International Green and Sustainable Computing Conference (IGSC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127941718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Li Li, Yunhao Bai, Xiaorui Wang, Mai Zheng, Feng Qin
{"title":"Selective checkpointing for minimizing recovery energy and efforts of smartphone apps","authors":"Li Li, Yunhao Bai, Xiaorui Wang, Mai Zheng, Feng Qin","doi":"10.1109/IGCC.2017.8323571","DOIUrl":"https://doi.org/10.1109/IGCC.2017.8323571","url":null,"abstract":"Unintended smartphone rebooting and unexpected shutdown (due to reasons like battery run outs, overheating, or automatic app upgrades) is annoying. What can be even worse is that a phone user has to restart, from the very beginning, the apps he or she was using when the phone got rebooted, because all the app states would be lost, especially when the number of apps in use is large. Hence, a recovery service is sorely needed for today's smartphones where apps are becoming increasingly complex. While checkpointing has long been used for desktop and laptop computers, such whole-system state preserving techniques cannot be applied to smartphones directly, due to the constraints of smartphones on energy, delay, and storage space. In this paper, we propose SmartCP, an intelligent checkpointing methodology, in order to reduce the energy required by a smartphone and the amount of efforts required by a user to recover the app states after the smartphone restarts. SmartCP selectively checkpoints the most important apps based on the apps' characteristics and predicted future usage, under the resource constraints of the phone. We propose a novel model that quantitatively analyzes the recovery energy and efforts of each category of smartphone apps and formulate selective checkpointing as a constrained optimization problem. We prototype SmartCP on Android and evaluate it using real-world traces as well as real user feedback. The results show that SmartCP outperforms two alternative app selection schemes by saving 28% more energy and 39% more recovery efforts on average.","PeriodicalId":133239,"journal":{"name":"2017 Eighth International Green and Sustainable Computing Conference (IGSC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134478598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Architecture independent integrated early performance and energy estimation","authors":"Antonino Tumeo","doi":"10.1109/IGCC.2017.8323602","DOIUrl":"https://doi.org/10.1109/IGCC.2017.8323602","url":null,"abstract":"The end of Dennard's scaling, coupled with the necessity to keep increasing computational performance in constrained power envelopes, is leading developers towards the need to optimize applications not only for performance, but also for energy consumption. In such a scenario, solutions that enable estimating performance and energy consumption of a program as early as possible, even during development and without the necessity to access the final target hardware, can become fundamental tools to reduce the design space, the optimization effort, and provide potential opportunities to automate the optimization process itself. In this position paper, we discuss the design of a performance and energy estimation framework based on a retargetable compiler. Our proposed approach targets the Intermediate Representation (IR) of the LLVM compiler. The IR based approach enables, after a model is built, estimation from a host different from the target architecture, even considering dynamic information. We present the rationale behind such a framework, identify opportunities and components readily available (such as static analysis, quick ways to add instrumentation for dynamic profiling, and the multiple backends), and aspects that still need further research efforts (such as more effective non-linear, or machine learning based models). We also discuss a hand-developed case study, based on a simple sparse matrix vector multiplication with a linear model, to motivate the needs for such a framework.","PeriodicalId":133239,"journal":{"name":"2017 Eighth International Green and Sustainable Computing Conference (IGSC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126171579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Dauwe, Rohan Jhaveri, S. Pasricha, A. A. Maciejewski, H. Siegel
{"title":"Optimizing checkpoint intervals for reduced energy use in exascale systems","authors":"D. Dauwe, Rohan Jhaveri, S. Pasricha, A. A. Maciejewski, H. Siegel","doi":"10.1109/IGCC.2017.8323598","DOIUrl":"https://doi.org/10.1109/IGCC.2017.8323598","url":null,"abstract":"In today's high performance computing (HPC) systems, the probability of applications experiencing failures has increased significantly with the increase in the number of system nodes. It is expected that exascale-sized systems are likely to operate with mean time between failures (MTBF) of as little as a few minutes, causing frequent interrupts in application execution as well as substantially greater energy costs in a system that will already consume large amounts of energy. State-of-the-art HPC resilience techniques proposed for use in these future systems complicate the energy problem further as the overhead associated with utilizing these techniques also further increases energy use. While work has been done that attempts to analyze and improve the energy use of systems utilizing resilience techniques, our work offers a new approach through the optimization of checkpoint interval lengths that allows a system designer the freedom to choose between intervals that optimize for application performance efficiency or energy use in both a traditional checkpoint and multilevel checkpoint approach to resilience. We create a set of equations able to optimize for either performance efficiency or energy use, demonstrate that distinct intervals exist when optimizing for either one metric or the other, and examine the sensitivity of this phenomena to changes in several system parameters and application characteristics.","PeriodicalId":133239,"journal":{"name":"2017 Eighth International Green and Sustainable Computing Conference (IGSC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116571600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Power and energy implications of misunderstanding DRAM","authors":"D. Kopta, E. Brunvand","doi":"10.1109/IGCC.2017.8323589","DOIUrl":"https://doi.org/10.1109/IGCC.2017.8323589","url":null,"abstract":"When optimizing for energy in a modern computing system, it is critical to understand the primary source of energy usage: the memory system. Performing effective optimization in a traditional memory system requires knowing something about the complex and subtle behavior of dynamic random access memory (DRAM). This includes understanding DRAM chip organization and functionality, the organization of chips and data on a dual inline memory module (DIMM), the structure of modern packaging options, and the behavior of the memory controller. In this position paper we describe some background of DRAM chip and system organization with some specific examples of how this knowledge can be used to enhance system behavior. We then give some examples of how understanding accurate DRAM behavior can influence energy and latency, and describe a detailed DRAM simulator (USIMM) that can be used to add high-fidelity DRAM models to system simulations. We use graphics hardware as a motivating example of a system that is both heavily reliant on the memory system, and that also has interesting latitude in terms of how the application accesses memory.","PeriodicalId":133239,"journal":{"name":"2017 Eighth International Green and Sustainable Computing Conference (IGSC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123466184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Energy-efficient primary/backup scheduling techniques for heterogeneous multicore systems","authors":"A. Roy, Hakan Aydin, Dakai Zhu","doi":"10.1109/IGCC.2017.8323569","DOIUrl":"https://doi.org/10.1109/IGCC.2017.8323569","url":null,"abstract":"In this paper, we consider energy-efficient and fault-tolerant scheduling of real-time tasks on heterogeneous multicore systems. Each task consists of a main copy and a backup copy which are scheduled on different cores, for fault tolerance purposes. Our framework deliberately delays the backup tasks in order to cancel them dynamically when the main task copies complete successfully (without faults). We identify and address two dimensions of the problem, i.e., partitioning tasks and determining processor voltage/frequency levels to minimize energy consumption. Our experimental results show that our proposed algorithms' performance levels are close to that of an ideal solution with optimal (but computationally prohibitive) partitioning and frequency assignment components.","PeriodicalId":133239,"journal":{"name":"2017 Eighth International Green and Sustainable Computing Conference (IGSC)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131424011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}