Power and energy implications of misunderstanding DRAM

Abstract

When optimizing for energy in a modern computing system, it is critical to understand the primary source of energy usage: the memory system. Performing effective optimization in a traditional memory system requires knowing something about the complex and subtle behavior of dynamic random access memory (DRAM). This includes understanding DRAM chip organization and functionality, the organization of chips and data on a dual inline memory module (DIMM), the structure of modern packaging options, and the behavior of the memory controller. In this position paper we describe some background of DRAM chip and system organization with some specific examples of how this knowledge can be used to enhance system behavior. We then give some examples of how understanding accurate DRAM behavior can influence energy and latency, and describe a detailed DRAM simulator (USIMM) that can be used to add high-fidelity DRAM models to system simulations. We use graphics hardware as a motivating example of a system that is both heavily reliant on the memory system, and that also has interesting latitude in terms of how the application accesses memory.