2015 33rd IEEE International Conference on Computer Design (ICCD)最新文献_第9页

Clustering-based revision debug in regression verification 回归验证中基于聚类的修正调试

2015 33rd IEEE International Conference on Computer Design (ICCD) Pub Date : 2015-10-18 DOI: 10.1109/ICCD.2015.7357081

Djordje Maksimovic, A. Veneris, Zissis Poulos

{"title":"Clustering-based revision debug in regression verification","authors":"Djordje Maksimovic, A. Veneris, Zissis Poulos","doi":"10.1109/ICCD.2015.7357081","DOIUrl":"https://doi.org/10.1109/ICCD.2015.7357081","url":null,"abstract":"Modern digital systems are growing in size and complexity, introducing significant organizational and verification challenges in the design cycle. Verification today takes as much as 70% of the design time with debugging being responsible for half of this effort. Automation has mitigated part of the resource-intensive nature of rectifying erroneous designs. Nevertheless, most tools target failures in isolation. Since regression verification can discover myriads of failures in one run, automation is also required to guide an engineer to rank them and expedite debugging. To address this growing regression pain, this paper presents a framework that utilizes traditional machine learning techniques along with historical data in version control systems and the results of functional debugging. Its aim is to rank revisions based on their likelihood of being responsible for a particular failure. Ranking prioritizes revisions that ought to be targeted first, and therefore it speeds-up the localization of the error source. This effectively reduces the number of debug iterations. Experiments on industrial designs demonstrate a 68% improvement in the ranking of actual erroneous revisions versus the ranking obtained through existing industrial methodologies. This benefit arrives with negligible run-time overhead.","PeriodicalId":129506,"journal":{"name":"2015 33rd IEEE International Conference on Computer Design (ICCD)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130390393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Side-channel power analysis of a GPU AES implementation 边信道功率分析的一个GPU AES实现

2015 33rd IEEE International Conference on Computer Design (ICCD) Pub Date : 2015-10-18 DOI: 10.1109/ICCD.2015.7357115

Chao Luo, Yunsi Fei, Pei Luo, Saoni Mukherjee, D. Kaeli

{"title":"Side-channel power analysis of a GPU AES implementation","authors":"Chao Luo, Yunsi Fei, Pei Luo, Saoni Mukherjee, D. Kaeli","doi":"10.1109/ICCD.2015.7357115","DOIUrl":"https://doi.org/10.1109/ICCD.2015.7357115","url":null,"abstract":"Graphics Processing Units (GPUs) have been used to run a range of cryptographic algorithms. The main reason to choose a GPU is to accelerate the encryption/decryption speed. Since GPUs are mainly used for graphics rendering, and only recently have they become a fully-programmable parallel computing device, there has been little attention paid to their vulnerability to side-channel attacks. In this paper we present a study of side-channel vulnerability on a state-of-the-art graphics processor. To the best of our knowledge, this is the first work that attempts to extract the secret key of a block cipher implemented to run on a GPU. We present a side-channel power analysis methodology to extract all of the last round key bytes of a CUDA AES (Advanced Encryption Standard) implementation run on an NVIDIA TESLA GPU. We describe how we capture power traces and evaluate the power consumption of a GPU. We then construct an appropriate power model for the GPU. We propose effective methods to sample and process the GPU power traces so that we can recover the secret key of AES. Our results show that parallel computing hardware systems such as a GPU are highly vulnerable targets to power-based side-channel attacks, and need to be hardened against side-channel threats.","PeriodicalId":129506,"journal":{"name":"2015 33rd IEEE International Conference on Computer Design (ICCD)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130824754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 57

A thermal adaptive scheme for reliable write operation on RRAM based architectures 基于RRAM架构的可靠写操作热自适应方案

2015 33rd IEEE International Conference on Computer Design (ICCD) Pub Date : 2015-10-18 DOI: 10.1109/ICCD.2015.7357126

F. García-Redondo, M. López-Vallejo, P. Ituero

引用次数: 4

Improving memristor memory with sneak current sharing 潜行电流共享改善忆阻器记忆

2015 33rd IEEE International Conference on Computer Design (ICCD) Pub Date : 2015-10-18 DOI: 10.1109/ICCD.2015.7357164

Manjunath Shevgoor, Naveen Muralimanohar, R. Balasubramonian, Yoocharn Jeon

{"title":"Improving memristor memory with sneak current sharing","authors":"Manjunath Shevgoor, Naveen Muralimanohar, R. Balasubramonian, Yoocharn Jeon","doi":"10.1109/ICCD.2015.7357164","DOIUrl":"https://doi.org/10.1109/ICCD.2015.7357164","url":null,"abstract":"Several memory vendors are pursuing different kinds of memory cells that can offer high density, non-volatility, high performance, and high endurance. There are several on-going efforts to architect main memory systems with these new NVMs that can compete with traditional DRAM systems. Each NVM has peculiarities that require new microarchitectures and protocols for memory access. In this work, we focus on memristor technology and the sneak currents inherent in memristor crossbar arrays. A read in state-of-the-art designs requires two consecutive reads; the first measures background sneak currents that can be factored out of the current measurement in the second read. This paper introduces a mechanism to reuse the background sneak current measurement for subsequent reads from the same column, thus introducing \"open-column\" semantics for memristor array access. We also examine a number of data mapping policies that allow the system to balance parallelism and locality. We conclude that on average, it is better to prioritize locality; our best design yields a 20% improvement in read latency and a 26% memory power reduction, relative to the state-of-the-art memristor baseline.","PeriodicalId":129506,"journal":{"name":"2015 33rd IEEE International Conference on Computer Design (ICCD)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116723324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 31

Increasing reconfigurability with memristive interconnects 增加记忆互连的可重构性

2015 33rd IEEE International Conference on Computer Design (ICCD) Pub Date : 2015-10-18 DOI: 10.1109/ICCD.2015.7357124

J. Demme, B. Rajendran, S. Nowick, S. Sethumadhavan

{"title":"Increasing reconfigurability with memristive interconnects","authors":"J. Demme, B. Rajendran, S. Nowick, S. Sethumadhavan","doi":"10.1109/ICCD.2015.7357124","DOIUrl":"https://doi.org/10.1109/ICCD.2015.7357124","url":null,"abstract":"The design of on-chip interconnects is largely governed by the size and power of the devices being connected. While large components like memory controllers, video decode accelerators, and cores can afford the overhead of a large packet switching NoC router, smaller components like adders or other ALUs cannot. Instead, they are typically connected via simple wires, limiting their runtime reconfigurability. The notable exception - FPGAs - use an interconnect which allows extreme reconfigurability, but the FPGA pays for it in area, power, and latency costs. Less costly reconfigurable interconnects, therefore, could allow hardware designers to expose more reconfigurability while limiting area and power costs. This paper presents the design of a high-radix circuit switching crossbar design using memristors. This design utilizes Phase Change Memory (PCM), overcoming some of its limitations such as leakage power and low voltage operation. The very small size of memristors shrinks the area, power, and latency of crossbars by up to 16x, 4.4x, and 2.4x, respectively, leaving little interconnect overhead but wiring overhead. As a tool for designers, memristive interconnects offer significant potential to increase runtime design flexibility.","PeriodicalId":129506,"journal":{"name":"2015 33rd IEEE International Conference on Computer Design (ICCD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115693865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Analytic processor model for fast design-space exploration 用于快速设计空间探索的解析处理器模型

2015 33rd IEEE International Conference on Computer Design (ICCD) Pub Date : 2015-10-18 DOI: 10.1109/ICCD.2015.7357136

R. Jongerius, Giovanni Mariani, Andreea Anghel, G. Dittmann, E. Vermij, H. Corporaal

引用次数: 14

Dynamic core scaling: Trading off performance and energy beyond DVFS 动态核心扩展:在DVFS之外权衡性能和能量

2015 33rd IEEE International Conference on Computer Design (ICCD) Pub Date : 2015-10-18 DOI: 10.1109/ICCD.2015.7357120

Wei Zhang, Hang Zhang, J. Lach

引用次数: 5

DLB: Dynamic lane borrowing for improving bandwidth and performance in Hybrid Memory Cube DLB:动态通道借用，用于提高混合内存立方体的带宽和性能

2015 33rd IEEE International Conference on Computer Design (ICCD) Pub Date : 2015-10-18 DOI: 10.1109/ICCD.2015.7357093

Xianwei Zhang, Youtao Zhang, Jun Yang

引用次数: 4

Methods for analysing and improving the fault resilience of delay-insensitive codes 延迟不敏感码的故障恢复分析与改进方法

2015 33rd IEEE International Conference on Computer Design (ICCD) Pub Date : 2015-10-18 DOI: 10.1109/ICCD.2015.7357160

J. Lechner, A. Steininger, F. Huemer

引用次数: 4

A testing platform for on-drone computation 无人机上计算测试平台

2015 33rd IEEE International Conference on Computer Design (ICCD) Pub Date : 2015-10-18 DOI: 10.1109/ICCD.2015.7357188

Wang Zhou, Dhruv Nair, O. Gunawan, T. V. Kessel, H. Hamann

引用次数: 6