{"title":"动态核心扩展:在DVFS之外权衡性能和能量","authors":"Wei Zhang, Hang Zhang, J. Lach","doi":"10.1109/ICCD.2015.7357120","DOIUrl":null,"url":null,"abstract":"Dynamic voltage and frequency scaling (DVFS) is commonly employed on modern superscalar processors to reduce energy when peak performance is not needed or allowed. As technology scales, the effectiveness of DVFS is limited by the shrinking viable supply voltage range. This work proposes dynamic core scaling (DCS) to extend performance-energy tradeoff capabilities in superscalar processors. DCS ensures that programs run at a given percentage of their maximum speed and, at the same time, minimizes energy consumption by dynamically adjusting the active superscalar datapath resources. Evaluations using an 8-way superscalar processor implemented on 45nm circuit infrastructure show that DCS is more effective in performance-energy tradeoffs than DVFS at the high performance end. When used together with DVFS, DCS saves an additional 20% of a full-size core's energy on average. At the minimum operating voltage, DVFS stops reducing energy, while DCS is still able to achieve an average of 46% further energy reduction.","PeriodicalId":129506,"journal":{"name":"2015 33rd IEEE International Conference on Computer Design (ICCD)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Dynamic core scaling: Trading off performance and energy beyond DVFS\",\"authors\":\"Wei Zhang, Hang Zhang, J. Lach\",\"doi\":\"10.1109/ICCD.2015.7357120\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Dynamic voltage and frequency scaling (DVFS) is commonly employed on modern superscalar processors to reduce energy when peak performance is not needed or allowed. As technology scales, the effectiveness of DVFS is limited by the shrinking viable supply voltage range. This work proposes dynamic core scaling (DCS) to extend performance-energy tradeoff capabilities in superscalar processors. DCS ensures that programs run at a given percentage of their maximum speed and, at the same time, minimizes energy consumption by dynamically adjusting the active superscalar datapath resources. Evaluations using an 8-way superscalar processor implemented on 45nm circuit infrastructure show that DCS is more effective in performance-energy tradeoffs than DVFS at the high performance end. When used together with DVFS, DCS saves an additional 20% of a full-size core's energy on average. At the minimum operating voltage, DVFS stops reducing energy, while DCS is still able to achieve an average of 46% further energy reduction.\",\"PeriodicalId\":129506,\"journal\":{\"name\":\"2015 33rd IEEE International Conference on Computer Design (ICCD)\",\"volume\":\"18 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-10-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 33rd IEEE International Conference on Computer Design (ICCD)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCD.2015.7357120\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 33rd IEEE International Conference on Computer Design (ICCD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCD.2015.7357120","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Dynamic core scaling: Trading off performance and energy beyond DVFS
Dynamic voltage and frequency scaling (DVFS) is commonly employed on modern superscalar processors to reduce energy when peak performance is not needed or allowed. As technology scales, the effectiveness of DVFS is limited by the shrinking viable supply voltage range. This work proposes dynamic core scaling (DCS) to extend performance-energy tradeoff capabilities in superscalar processors. DCS ensures that programs run at a given percentage of their maximum speed and, at the same time, minimizes energy consumption by dynamically adjusting the active superscalar datapath resources. Evaluations using an 8-way superscalar processor implemented on 45nm circuit infrastructure show that DCS is more effective in performance-energy tradeoffs than DVFS at the high performance end. When used together with DVFS, DCS saves an additional 20% of a full-size core's energy on average. At the minimum operating voltage, DVFS stops reducing energy, while DCS is still able to achieve an average of 46% further energy reduction.