58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526)最新文献_第7页

New device models of quantum well infrared photodetectors 量子阱红外探测器的新器件模型

58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526) Pub Date : 2000-06-19 DOI: 10.1109/DRC.2000.877082

J. Pan

引用次数: 0

Switching characteristics of 3 kV 4H-SiC GTO thyristors 3kv 4H-SiC GTO晶闸管的开关特性

58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526) Pub Date : 2000-06-19 DOI: 10.1109/DRC.2000.877121

J. Fedison, T. Chow, A. Agarwal, S. Ryu, R. Singh, O. Kordina, J. Palmour

引用次数: 8

Five-terminal amorphous silicon thin-film transistor structure 五端非晶硅薄膜晶体管结构

58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526) Pub Date : 2000-06-19 DOI: 10.1109/DRC.2000.877088

S. Martin, Y. Feillens, J. Kanicki

{"title":"Five-terminal amorphous silicon thin-film transistor structure","authors":"S. Martin, Y. Feillens, J. Kanicki","doi":"10.1109/DRC.2000.877088","DOIUrl":"https://doi.org/10.1109/DRC.2000.877088","url":null,"abstract":"Hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) are widely used in large area electronics applications like active-matrix liquid-crystal displays (AMLCDs) or in or X-ray and optical sensors. TFTs often suffer from source and drain series resistances that perturbate the intrinsic channel performance, especially in the cases of poor source and drain contacts or high density of states present in the a-Si:H electronic gap. To accurately evaluate the TFT intrinsic properties without the influence of the parasitic series resistances, we have previously introduced the five-terminal TFT (FT TFT), or gated-four probe TFT (GFP TFT) structure (Chen and Kanicki, 1997 and 1998). This device has two additional electrodes fabricated between the source and drain contacts. Such a structure is expected to allow for evaluation of the potential difference along the conduction channel, assuming that the potential difference is the same at the conduction channel interface (a-Si:H/a-SiN/sub x/:H) and at the back interface (substrate/a-Si:H). We show in this paper that, indeed, FT TFTs can be used to accurately study TFT conduction channel intrinsic properties.","PeriodicalId":126654,"journal":{"name":"58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526)","volume":"162 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130046328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Low-noise SiGe pMODFETs on sapphire with 116 GHz f/sub max/ 蓝宝石上低噪声SiGe pmodfet, 116ghz f/sub max/

58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526) Pub Date : 2000-06-19 DOI: 10.1109/DRC.2000.877076

S. Koester, R. Hammond, J. Chu, P. Mooney, J. Ott, C. Webster, I. Lagnado, P. de la Houssaye

{"title":"Low-noise SiGe pMODFETs on sapphire with 116 GHz f/sub max/","authors":"S. Koester, R. Hammond, J. Chu, P. Mooney, J. Ott, C. Webster, I. Lagnado, P. de la Houssaye","doi":"10.1109/DRC.2000.877076","DOIUrl":"https://doi.org/10.1109/DRC.2000.877076","url":null,"abstract":"Recent advances in SiGe MODFET technology indicate that these devices may have promise for future high-speed analog communications applications (Adesida et al, 1997; Konig et al, 1998). However, losses and isolation problems due to the conducting Si substrate represent a serious disadvantage compared to III-V devices that utilize semi-insulating substrates. The use of insulating substrates such as sapphire is a potential solution to this problem, and previous results on Si and pseudomorphic SiGe-channel MOSFETs fabricated on silicon-on-sapphire (SOS) wafers have been encouraging (Johnson et al, 1998; Mathew et al, 1999). However, SiGe MODFETs require relaxed SiGe buffer layers, and the growth of high-quality relaxed SiGe on sapphire or SOS substrates has not previously been demonstrated. In this paper, we present the results of 0.1 /spl mu/m gate length pMODFETs fabricated on high-mobility Si/sub 0.2/Ge/sub 0.8/-Si/sub 0.7/Ge/sub 0.3/ quantum wells grown on SOS wafers. These devices displayed a power gain cut-off frequency (f/sub max/) of 116 GHz, and minimum noise figure (F/sub mm/) of 2.5 dB at 20 GHz. To our knowledge, these values are the best reported to date for pFETs in any material system.","PeriodicalId":126654,"journal":{"name":"58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130120776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Monolithic integration of InAlAs-InGaAs-InP HEMTs and InAs-AlSb-GaSb resonant interband tunneling diodes (RITDs) for high speed integrated circuits 高速集成电路中inas - ingaas - inp hemt和InAs-AlSb-GaSb谐振带间隧道二极管(ritd)的单片集成

58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526) Pub Date : 2000-06-19 DOI: 10.1109/DRC.2000.877132

P. Fay, J. Lu, Y. Xu, G. Bernstein, D. Chow, J. Schulman, H. Dunlap, H. De los Santos

{"title":"Monolithic integration of InAlAs-InGaAs-InP HEMTs and InAs-AlSb-GaSb resonant interband tunneling diodes (RITDs) for high speed integrated circuits","authors":"P. Fay, J. Lu, Y. Xu, G. Bernstein, D. Chow, J. Schulman, H. Dunlap, H. De los Santos","doi":"10.1109/DRC.2000.877132","DOIUrl":"https://doi.org/10.1109/DRC.2000.877132","url":null,"abstract":"We report for the first time the monolithic integration of high-speed submicron gate length InAlAs-InGaAs-InP HEMTs with InAs-AlSb-GaSb resonant interband tunneling diodes (RITDs) for ultra-high-speed IC applications. The epitaxial layers for the integrated RITD/HEMT device process were deposited by molecular beam epitaxy (MBE) on 2\" semi-insulating InP substrates. Critical aspects of MBE growth process development include: (1) nucleation of a smooth, strain-relaxed InAs n/sup +/ buffer layer on top of the InGaAs-InAlAs HEMT device layers to provide a growth template and bottom contact for the InAs-AlSb-GaSb RITD active layers, and (2) two AlAs etch stop layers to allow uniform removal of the RITD layers for HEMT processing and uniform gate recess etching. In situ substrate temperature control using an absorption edge spectroscopy sensor was used to nucleate the strain-relaxed InAs buffer at a substrate temperature of 400/spl deg/C followed by heating to 480/spl deg/C for growth of a 150 nm buffer layer. A smooth, thin buffer layer is advantageous for integration of the RITD and HEMT devices in that the RITD device mesas can be short (0.4 /spl mu/m), yielding a relatively planar process geometry. A 50 nm-thick lattice-matched InGaAs layer was deposited between the RITD/HEMT isolation AlAs etch stop layer and the strain-relaxed InAs buffer layer to ensure the structural integrity of the etch stop layer. A carrier concentration of 2.7 10/sup 12/ cm/sup -2/ and mobility of 9500 cm/sup 2//Vs in the HEMT channel were measured. These values are comparable to a control HEMT-only heterostructure.","PeriodicalId":126654,"journal":{"name":"58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134421769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Dark current reduction and operational wavelength shift in normal incidence InAs-GaAs QDIPs through the introduction of AlGaAs layers in the active region of the detector 通过在探测器有源区引入AlGaAs层，在正常入射的InAs-GaAs qdip中减小暗电流和工作波长位移

58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526) Pub Date : 2000-06-19 DOI: 10.1109/DRC.2000.877135

O. Baklenov, Z.H. Chen, E.T. Kim, I. Mukhametzhanov, A. Madhukar, F. Ma, Z. Ye, B. Yang, J. Campbell

{"title":"Dark current reduction and operational wavelength shift in normal incidence InAs-GaAs QDIPs through the introduction of AlGaAs layers in the active region of the detector","authors":"O. Baklenov, Z.H. Chen, E.T. Kim, I. Mukhametzhanov, A. Madhukar, F. Ma, Z. Ye, B. Yang, J. Campbell","doi":"10.1109/DRC.2000.877135","DOIUrl":"https://doi.org/10.1109/DRC.2000.877135","url":null,"abstract":"Self-assembled quantum dots (SAQDs) are an attractive alternative to quantum wells (QWs) for near to long-wavelength infrared photodetector applications. Due to the 3D carrier confinement and lack of symmetry-imposed selection rules, SAQDs are intrinsically sensitive to normal incidence photoexcitation and predicted to have lower dark current and higher sensitivity compared to QW intersubband photodetectors (Ryzhii, 1996), though the filling factor is substantially less for QDs than that for QWs. Initial reported results on normal-incidence QD intersubband photodetectors (e.g. Pan et al, 1998) offer encouragement for further investigations. In this report, we demonstrate the ability to reduce the dark current and to shift the operational wavelength of InAs-GaAs QD infrared photodetectors (QDIPs) through the introduction of AlGaAs barriers in the active region of the detector structure. AlGaAs layers are placed between the QD layers to act as blocking barriers for the dark current contribution through the region between the QDs.","PeriodicalId":126654,"journal":{"name":"58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130261468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Single electron memory utilizing nano-crystalline Si over short-channel silicon-on-insulator transistors 在短通道绝缘体上硅晶体管上利用纳米晶硅的单电子存储器

58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526) Pub Date : 2000-06-19 DOI: 10.1109/DRC.2000.877127

B. Hinds, A. Dutta, F. Yun, T. Yamanaka, S. Hatanani, S. Oda

{"title":"Single electron memory utilizing nano-crystalline Si over short-channel silicon-on-insulator transistors","authors":"B. Hinds, A. Dutta, F. Yun, T. Yamanaka, S. Hatanani, S. Oda","doi":"10.1109/DRC.2000.877127","DOIUrl":"https://doi.org/10.1109/DRC.2000.877127","url":null,"abstract":"A promising approach for high density/low power consumption memory devices is to store a single charge in a nano-scale memory node, which affects electron transport in a nearby channel. Advantages of this design are room temperature operation and self limiting charge storage by Coulomb repulsion. Two notable approaches to this concept are nanocrystalline-Si (nc-Si) acting as a floating gate in a large area MOSFET (Tiwari et al., 1996) and a single polysilicon dot defined by e-beam lithography over a narrow SOI channel (Guo et al., 1997). A device which is sensitive to a single charge while using a method of nc-Si dot fabrication that is scalable to VLSI is required. Single electron memory devices based on two approaches of forming nc-Si with large area deposition processes are reported here. To make the active region of the device sensitive to a single charged dot, narrow channels (40 nm length by 30 nm width) are defined by e-beam lithography of thin (20 nm) SOI. The first approach for nc-Si synthesis is gas phase nucleation and growth by pulsed-source remote PECVD, which form 8/spl plusmn/1 nm diameter nc-Si dots (Ifuku et al., 1997). The second approach for scalable nc-Si formation is to deposit a thin film of SiO/sub x/ (x<2). Annealing of this film results in high density 3-8 nm nc-Si dots isolated from each other by a SiO/sub 2/ tunnel barrier (Hamasaki et al., 1978).","PeriodicalId":126654,"journal":{"name":"58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134344720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

HBT on LEO GaN

58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526) Pub Date : 2000-06-19 DOI: 10.1109/DRC.2000.877101

L. McCarthy, Y. Smorchkova, P. Fini, H. Xing, M. Rodwell, J. Speck, S. Denbaars, U. Mishra

{"title":"HBT on LEO GaN","authors":"L. McCarthy, Y. Smorchkova, P. Fini, H. Xing, M. Rodwell, J. Speck, S. Denbaars, U. Mishra","doi":"10.1109/DRC.2000.877101","DOIUrl":"https://doi.org/10.1109/DRC.2000.877101","url":null,"abstract":"Dramatic progress in GaN electronics has led to increased interest in bipolar transistors. Although there have been reports of GaN bipolars from several groups, the development of the GaN bipolar transistor is still in its fundamental stages. In the case of GaN, the usual correlation between common base, Gummel, and common emitter characteristics does not exist due to significant collector-emitter leakage, leaving only the common emitter characteristic as a reliable measure of DC device performance. We identify the source of this leakage as threading dislocations and clarify the effect of this leakage on the transistor DC characteristics. Furthermore, we conclude from various growth structures and methods of device fabrication that the electron lifetime in the neutral base is currently the limiting factor in GaN NPN transistor performance. Typical GaN material has high threading dislocation densities, 10/sup 7/-10/sup 9/ cm/sup -2/, due to lattice mismatch with the substrate, typically sapphire or SiC. To study the effects of threading dislocations on GaN bipolar transistors, we have fabricated devices on material grown using the lateral epitaxial overgrowth technique, LEO. To the authors' knowledge, this is the first demonstration of GaN bipolar transistors grown on nondislocated material. The LEO substrate allows us to compare devices grown on material with a negligible dislocation density with those grown on a standard template.","PeriodicalId":126654,"journal":{"name":"58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122846724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Development of a novel micromachined magnetostatic membrane actuator 新型微机械静磁膜致动器的研制

58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526) Pub Date : 2000-06-19 DOI: 10.1109/DRC.2000.877110

M. Khoo, Chang Liu

引用次数: 7

Microelectronic arrays and electric field assisted self-assembly of component structures for micro/nanofabrication applications 微电子阵列和电场辅助元件结构自组装在微/纳米制造中的应用

58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526) Pub Date : 1900-01-01 DOI: 10.1109/DRC.2000.877102

M. Heller

{"title":"Microelectronic arrays and electric field assisted self-assembly of component structures for micro/nanofabrication applications","authors":"M. Heller","doi":"10.1109/DRC.2000.877102","DOIUrl":"https://doi.org/10.1109/DRC.2000.877102","url":null,"abstract":"In general, molecular or nanoelectronic devices and systems are envisioned as the near-term applications of nanotechnology. The main issue with enabling molecular electronics is likely to be the development of a viable technology which will allow molecular or nanoelectronic components to be assembled and interconnected into useful logic/memory devices and systems. We are currently involved in the development of active microelectronic DNA arrays for applications in genomic research and DNA diagnostics. When specific DNA hybridization reactions are carried out on the array, the device is actually using electric fields to direct the self-assembly of DNA molecules at the specified microlocation on the chip surface. Microelectronic arrays have been used to demonstrate the organization of complex fluorescent DNA molecular structures and mechanisms within selected microlocations on the array device. Thus, in principle these active devices are serving as semiconductor hosts or motherboards for the nanofabrication of DNA derived component molecules into more complex structures. While we have been primarily developing active microelectronic chips for genomic research and DNA diagnostic applications, their ability to transport nanostructures, cells, and micron-size structures has not escaped our attention. Thus, for nanofabrication applications we believe that these microelectronic arrays can serve as host substrates for the organization of various DNA derived components into more complex 2D/3D structures.","PeriodicalId":126654,"journal":{"name":"58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132277625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0