58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526)最新文献

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Modeling high k gate current from p-type Si inversion layers 用p型硅反转层模拟高k栅极电流
58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526) Pub Date : 2000-06-19 DOI: 10.1109/DRC.2000.877090
Y.-Y. Fan, S. Mudanai, W. Qi, J.C. Lee, A. Tasch, L. Register, S. Banerjee
{"title":"Modeling high k gate current from p-type Si inversion layers","authors":"Y.-Y. Fan, S. Mudanai, W. Qi, J.C. Lee, A. Tasch, L. Register, S. Banerjee","doi":"10.1109/DRC.2000.877090","DOIUrl":"https://doi.org/10.1109/DRC.2000.877090","url":null,"abstract":"High permittivity (high k) materials are being considered as replacement for SiO/sub 2/ as the gate dielectric since the higher physical thickness can reduce the direct tunneling current while retaining the low equivalent oxide thickness (EOT) required by next-generation MOSFETs. An unavoidable silicate layer or an intentional buffer layer such as SiO/sub 2/ to improve interface properties is always found between the high k layer and silicon substrate. In this paper, we explore issues that need to be considered when modeling gate current in such high k gate stack structures. We have studied the gate current due to electron tunneling from the p-type Si inversion layer.","PeriodicalId":126654,"journal":{"name":"58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132069240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Vertical P-MOSFETs with heterojunction between source/drain and channel 源极/漏极和沟道之间具有异质结的垂直p - mosfet
58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526) Pub Date : 2000-06-19 DOI: 10.1109/DRC.2000.877073
Xiangdong Chen, Q. Ouyang, K. C. Liu, Zhong Shi, A. Tasch, Sanjay K. Banerjee
{"title":"Vertical P-MOSFETs with heterojunction between source/drain and channel","authors":"Xiangdong Chen, Q. Ouyang, K. C. Liu, Zhong Shi, A. Tasch, Sanjay K. Banerjee","doi":"10.1109/DRC.2000.877073","DOIUrl":"https://doi.org/10.1109/DRC.2000.877073","url":null,"abstract":"The growth of high quality strained SiGe-Si and SiGeC-Si heterostructures allows incorporation of band gap engineering into Si technology, which can be used to improve device characteristics. A heterojunction MOSFET (HJMOSFET) structure has been proposed in which the large valence band offset at SiGe-Si heterojunctions reduces the punchthrough and DIBL for P-MOSFETs (Hareland et al, 1993). Vertical MOSFETs allow more freedom in terms of band gap engineering, and the channel length is not limited by the lithography (Liu et al, 1998). In this paper, we show experimentally that the heterojunction at the source can be used to suppress the floating body effect and short channel effect. Vertical P-MOSFETs with strained SiGe and SiGeC sources have been fabricated with 60-75 nm effective channel lengths. The electrical characteristics of the devices are compared with those of control Si devices and with simulation results.","PeriodicalId":126654,"journal":{"name":"58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127555925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Wideband AlGaN-GaN HEMTs on SiC for low noise applications 用于低噪声应用的SiC上的宽带AlGaN-GaN hemt
58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526) Pub Date : 2000-06-19 DOI: 10.1109/DRC.2000.877079
Wu Lu, J. Yang, M.A. Khan, I. Adesida
{"title":"Wideband AlGaN-GaN HEMTs on SiC for low noise applications","authors":"Wu Lu, J. Yang, M.A. Khan, I. Adesida","doi":"10.1109/DRC.2000.877079","DOIUrl":"https://doi.org/10.1109/DRC.2000.877079","url":null,"abstract":"AlGaN-GaN high electron mobility transistors (HEMTs) have attracted attention because of their extremely high current drive capability and high power performance. Although these GaN-based FETs are primarily considered for high power and high temperature applications, it is important to investigate their microwave noise characteristics. Indeed, the only report in literature (Ping et al, Electron. Lett. vol. 36, pp. 175-176, 2000) to date has shown that AlGaN-GaN HEMTs do have respectable noise properties that are comparable to those of AlGaAs-GaAs HEMTs. Specifically, we have recently reported on 0.25 /spl mu/m AlGaN-GaN HEMTs with a minimum noise figure (NF/sub min/) of 0.77 dB at 5 GHz and a NF/sub min/ of 1.06 dB at 10 GHz. These results are quite counter-intuitive to what might be expected due to the material properties, and especially the defect density, of GaN. However, the results do motivate further investigations of the noise properties of AlGaN-GaN HEMTs. In this paper, we report our latest results on DC, RF, and high frequency noise characteristics of AlGaN-GaN HEMTs, demonstrating a record bandwidth of 100 GHz and NF/sub min/ of 0.53 dB at 8 GHz.","PeriodicalId":126654,"journal":{"name":"58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526)","volume":"127 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132886627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
AlGaN-GaN HEMTs and HBTs for microwave power 用于微波功率的gan - gan hemt和HBTs
58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526) Pub Date : 2000-06-19 DOI: 10.1109/DRC.2000.877077
U. Mishra, R. Ventury, L. McCarthy, Y. Smorchkova, S. Keller, H. Xing, N. Zhang, J. Speck, R. York, S. Denbaars, Y. Wu, P. Parikh, P. Chavarkar
{"title":"AlGaN-GaN HEMTs and HBTs for microwave power","authors":"U. Mishra, R. Ventury, L. McCarthy, Y. Smorchkova, S. Keller, H. Xing, N. Zhang, J. Speck, R. York, S. Denbaars, Y. Wu, P. Parikh, P. Chavarkar","doi":"10.1109/DRC.2000.877077","DOIUrl":"https://doi.org/10.1109/DRC.2000.877077","url":null,"abstract":"Summary form only given. The AlGaN-GaN based material system offers the three most important materials properties required for efficient microwave power generation: very high breakdown electric field (/spl sim/2 MV/cm), high electron mobility and velocity (/spl mu//sub c//spl sim/1000 cm/sup 2//spl middot/V/sup -1/s/sup -1/ and v/sub s//spl sim/2/spl times/10/sup 7/ cm/spl middot/s/sup -1/ in bulk materials) and heterojunction technology to optimize device design. This has led to the rapid development of AlGaN-GaN HEMTs, grown heteroepitaxially on either sapphire or SiC substrates. AlGaN-GaN HBTs also show promise for power amplifier and switching applications. Inherent strengths of the HBT structure include high current densities and low phase noise, as well as improved linearity and threshold control. The progress in HEMT DC and RF performance has been spectacular and the possibility of insertion into high power systems is a distinct possibility. The HBTs continue to have to battle problems with p-type doping and associated processing difficulties. However, sustained progress in engineering around this problem holds promise for the future.","PeriodicalId":126654,"journal":{"name":"58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132197682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design optimization of stacked gate oxides with easy evaluation of gate leakage in deep submicron MOSFET 深亚微米MOSFET中易于评估栅漏的堆叠栅氧化物设计优化
58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526) Pub Date : 2000-06-19 DOI: 10.1109/DRC.2000.877093
Jinlong Zhang, J. Yuan, Yi Ma, A. Oates
{"title":"Design optimization of stacked gate oxides with easy evaluation of gate leakage in deep submicron MOSFET","authors":"Jinlong Zhang, J. Yuan, Yi Ma, A. Oates","doi":"10.1109/DRC.2000.877093","DOIUrl":"https://doi.org/10.1109/DRC.2000.877093","url":null,"abstract":"As the gate oxide is scaled down to 2 nm and below in a deep submicron CMOS transistor, direct tunneling and surface roughness seriously degrade the device performance. Alternative high-k materials are then considered to replace silicon dioxide. To achieve better interface quality and improve short channel effects, an extremely thin buffer layer of lower-k has been found favorable between the high-k layer and the silicon substrate. This leads to stacked gate architectures. The evaluation, however, of the gate leakage through such a complex potential barrier becomes an issue. Although a tedious numerical method may be employed (Ricco and Azbel, 1984), it is not necessary for many cases where an approximate analytical solution can offer valuable insights into the leakage problem and quick assistance for design consideration. In this work, we propose a simple method to evaluate the tunneling current through a double barrier for the first time. Accordingly, we study the design optimization of the architectures.","PeriodicalId":126654,"journal":{"name":"58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133766666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low threshold 1.3 /spl mu/m GaAsSb lasers on GaAs substrates GaAs衬底上的低阈值1.3 /spl μ m GaAsSb激光器
58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526) Pub Date : 2000-06-19 DOI: 10.1109/DRC.2000.877115
O. Blum, J. Klem
{"title":"Low threshold 1.3 /spl mu/m GaAsSb lasers on GaAs substrates","authors":"O. Blum, J. Klem","doi":"10.1109/DRC.2000.877115","DOIUrl":"https://doi.org/10.1109/DRC.2000.877115","url":null,"abstract":"Summary form only given. Vertical-cavity surface-emitting lasers (VCSELs) operating at 1.3 /spl mu/m are of great interest for optical interconnect and communication applications. It is desirable to grow VCSELs on GaAs substrates due to well developed DBRs, ease of processing and accessibility of the oxidation technology available in GaAs/AlGaAs. Recently, significant effort has been dedicated to development of 1.3 /spl mu/m emitting active regions on GaAs substrates. We report room temperature, pulsed operation of SQW compressively strained type-II GaAsSb-InGaAs edge emitting lasers grown by molecular beam epitaxy on GaAs substrates. All data is measured on broad area, gain guided structures at room temperature. For a 1500 /spl mu/m long and 75 /spl mu/m wide laser, lasing occurs at 1.29 /spl mu/m, although electroluminescence peaks near 1.36 /spl mu/m at low injection currents. Similar blue shifts have been observed in type II structures (Peter et al., 1998) or in compositionally modulated materials (Fouquet et al., 1990). For a 2000 /spl mu/m/spl times/100 /spl mu/m device, average threshold currents were found to be 0.75 A with an average threshold current density of 380 A/cm/sup 2/. We measured an average slope efficiency of 14%. The threshold current density extrapolated for an infinite resonator length (for a 75 /spl mu/m wide laser) was found to be 120 A/cm/sup 2/. We also measured the characteristic temperature T/sub 0/ for these lasers and found it to be 60 K.","PeriodicalId":126654,"journal":{"name":"58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116863886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Reliability and modeling of GaN-based light emitting diode 氮化镓基发光二极管的可靠性与建模
58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526) Pub Date : 2000-06-19 DOI: 10.1109/DRC.2000.877095
Hyun-Soo Kim, Ji-Myon Lee, C. Huh, Sang‐Woo Kim, Dong-Joon Kim, Seong-Ju Park, H. Hwang
{"title":"Reliability and modeling of GaN-based light emitting diode","authors":"Hyun-Soo Kim, Ji-Myon Lee, C. Huh, Sang‐Woo Kim, Dong-Joon Kim, Seong-Ju Park, H. Hwang","doi":"10.1109/DRC.2000.877095","DOIUrl":"https://doi.org/10.1109/DRC.2000.877095","url":null,"abstract":"To date, a considerable body of data has been published relative to III-V nitride light emitting diodes. These diodes typically employ a lateral carrier injection type structure due to an insulating sapphire substrate. The use of a lateral carrier injection type structure, however, can lead to nonuniform current spreading due to difficulties in growing a high quality material (Eliashevich et al, 1999). In this regard, we report on an attempt to develop a model for uniform current spreading during LED performance.","PeriodicalId":126654,"journal":{"name":"58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526)","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126940115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Multiple-valued memory operation in SiN-based single-electron memory 基于sin的单电子存储器中的多值存储操作
58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526) Pub Date : 2000-06-19 DOI: 10.1109/DRC.2000.877128
H. Sunamura, H. Kawaura, T. Sakamoto, T. Baba
{"title":"Multiple-valued memory operation in SiN-based single-electron memory","authors":"H. Sunamura, H. Kawaura, T. Sakamoto, T. Baba","doi":"10.1109/DRC.2000.877128","DOIUrl":"https://doi.org/10.1109/DRC.2000.877128","url":null,"abstract":"Multiple-valued memory operation is one of the keys for future high-density memory devices since it significantly increases memory capacity per unit area. We previously reported a single electron memory device that utilizes traps in a silicon nitride (SiN) layer as the memory node and an ultra-sensitive Al/AlO/sub x/ single-electron transistor (SET) for readout (Sunarmura et al., 1999). In this work, we propose a new device structure in which a new layered structure is designed so that only electrons can participate in the device characteristics. With this new device structure, we successfully achieve multiple-valued single-electron memory operation of up to nine values for the first time. An oscillating behavior in SET output current (I/sub SET/) during write/read processes due to electron trapping/detrapping at the traps is used to represent multiple values.","PeriodicalId":126654,"journal":{"name":"58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114155409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A novel sub-10 nm transistor 一种新型的10纳米以下晶体管
58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526) Pub Date : 2000-06-19 DOI: 10.1109/DRC.2000.877094
P. Kalavade, K. Saraswat
{"title":"A novel sub-10 nm transistor","authors":"P. Kalavade, K. Saraswat","doi":"10.1109/DRC.2000.877094","DOIUrl":"https://doi.org/10.1109/DRC.2000.877094","url":null,"abstract":"We report on a novel transistor structure which has the special features of (1) precise gate length control through a deposited film thickness; (2) an ultra-thin body for suppression of short channel effects; (3) raised source/drain (S/D) to reduce parasitic resistance; (4) a gate-last process compatible with high-k low temperature dielectrics; and (5) a low thermal budget process. Using this structure, transistors with a 9 nm gate length have been fabricated without the use of advanced lithography. To the authors' knowledge, this is the smallest reported functional NMOS transistor.","PeriodicalId":126654,"journal":{"name":"58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116574298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design and characterization of GaAs-Ga/sub 0.89/In/sub 0.11/N/sub 0.02/As/sub 0.98/-GaAs NpN double heterojunction bipolar transistors with low turn-on voltage 低导通电压GaAs-Ga/sub 0.89/In/sub 0.11/N/sub 0.02/As/sub 0.98/-GaAs NpN双极异质结晶体管的设计与表征
58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526) Pub Date : 2000-06-19 DOI: 10.1109/DRC.2000.877125
R. Welty, H. Xin, K. Mochizuki, C. Tu, P. Asbeck
{"title":"Design and characterization of GaAs-Ga/sub 0.89/In/sub 0.11/N/sub 0.02/As/sub 0.98/-GaAs NpN double heterojunction bipolar transistors with low turn-on voltage","authors":"R. Welty, H. Xin, K. Mochizuki, C. Tu, P. Asbeck","doi":"10.1109/DRC.2000.877125","DOIUrl":"https://doi.org/10.1109/DRC.2000.877125","url":null,"abstract":"GaAs-based heterojunction bipolar transistors (HBTs) have achieved widespread in high performance microwave and digital applications. However, they have a large base-emitter turn-on voltage V/sub BE/ of 1.4 V (at high current density). It is important to develop techniques to reduce V/sub BE/, particularly for low power applications. In this work, NpN double heterojunction bipolar transistors (DHBTs) were fabricated on a GaAs substrate with a Ga/sub 0.89/In/sub 0.11/N/sub 0.02/As/sub 0.98/ base that has a bandgap energy of 0.98 eV. These devices have a turn-on voltage V/sub BE/ that is 0.4 V lower than that of their GaAs base counterparts, allowing operation with lower power supply voltage and reduced power dissipation. To overcome the large conduction band discontinuity between GaAs and Ga/sub 0.89/In/sub 0.11/N/sub 0.02/As/sub 0.98/, both chirped compositional grading and delta doping were employed. In this paper, we report our first Ga(0.89)In/sub 0.11/N/sub 0.02/As/sub 0.98/-base DHBT results, which has a substantially greater V/sub BE/ reduction. The samples were grown by GSMBE with thermally cracked arsine and RF-plasma nitrogen radical beam as the arsenic and nitrogen source, respectively.","PeriodicalId":126654,"journal":{"name":"58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122903452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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