ITherm'98. Sixth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.98CH36208)最新文献

Void-effect modeling of flip-chip encapsulation on ceramic substrate 陶瓷基板上倒装芯片封装的空隙效应建模

ITherm'98. Sixth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.98CH36208) Pub Date : 1998-05-27 DOI: 10.1109/ITHERM.1998.689555

T. Niu, B. Sammakia, S. Sathe

引用次数: 11

Solder joint reliability of high I/O ceramic-ball-grid arrays and ceramic quad-flat packs in computer environments: The PowerPC 603/sup TM/ and PowerPC 604/sup TM/ microprocessors 计算机环境中高 I/O 陶瓷球栅阵列和陶瓷四扁平封装的焊点可靠性：PowerPC 603/sup TM/ 和 PowerPC 604/sup TM/ 微处理器

ITherm'98. Sixth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.98CH36208) Pub Date : 1998-05-27 DOI: 10.1109/ITHERM.1998.689546

D. Gerke, G. Kromann, A. Srikantappa

{"title":"Solder joint reliability of high I/O ceramic-ball-grid arrays and ceramic quad-flat packs in computer environments: The PowerPC 603/sup TM/ and PowerPC 604/sup TM/ microprocessors","authors":"D. Gerke, G. Kromann, A. Srikantappa","doi":"10.1109/ITHERM.1998.689546","DOIUrl":"https://doi.org/10.1109/ITHERM.1998.689546","url":null,"abstract":"Recent trends in wafer fabrication techniques have produced devices with smaller feature dimensions, increasing gate count and increased chip I/Os. This trend has placed increased emphasis on microelectronic packaging. Surface-mountable packages such as the ceramic quad-flat-pack (CQFP) have provided solutions for many high I/O package issues. As the I/O count increases, the pitch has been driven down to the point where other solutions become attractive. Surface-mountable ceramic-ball-grid array (CBGA) packages have proven to be good solutions in a variety of applications as designers seek to maximize electrical performance, reduce PCB real estate, and improve manufacturing process yields. In support of the PowerPC 603 and PowerPC 604 microprocessors, 21 mm CBGA (255 I/Os) and 32 mm (240 I/Os) and 30 mm (304 I/Os) CQFPs are being used. Both package types successfully meet computer environment applications. This paper describes test board assembly processes, accelerated thermal stress test set-up, and solder joint failure criteria. Failure mechanisms for both packaging technologies are also presented. The packages discussed in this paper were subjected to two accelerated thermal cycling conditions: 0 to 100/spl deg/C and -40 to 125/spl deg/C. The failure data are plotted using Weibull distributions. The accelerated failure distributions were used to predict failure distributions in application space for typical PowerPC 603 and PowerPC 604 microprocessor computer environments.","PeriodicalId":125267,"journal":{"name":"ITherm'98. Sixth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.98CH36208)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126929161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Numerical and experimental analysis of natural convection in a cavity with flush mounted heat sources on a side wall 侧壁面装有嵌入式热源的空腔内自然对流的数值与实验分析

ITherm'98. Sixth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.98CH36208) Pub Date : 1998-05-27 DOI: 10.1109/ITHERM.1998.689530

R. Ramos, T. Dias, L. Milanez

引用次数: 4

Steady state and transient thermal analysis of chip scale packages 芯片级封装的稳态和瞬态热分析

ITherm'98. Sixth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.98CH36208) Pub Date : 1998-05-27 DOI: 10.1109/ITHERM.1998.689521

B. Chambers, T.Y. Tom Lee, W. Blood

{"title":"Steady state and transient thermal analysis of chip scale packages","authors":"B. Chambers, T.Y. Tom Lee, W. Blood","doi":"10.1109/ITHERM.1998.689521","DOIUrl":"https://doi.org/10.1109/ITHERM.1998.689521","url":null,"abstract":"This paper summarizes a study of chip scale packages (CSPs) to determine their maximum allowable power dissipation within typical system level environments. These results can be used to determine the applicability of utilizing CSPs from the standpoint of die power dissipation. Both steady state and transient thermal performance is covered in this study. The steady state portion used in-house software, while closed-form solutions were used for the transient analysis. The steady state power limit, while governed by a number of parameters, is dependent mainly upon system level parameters (heat sinking, cooling mode, i.e. natural or forced convection, and PCB power loading). Thermal enhancement features (e.g. thermal vias and bumps) are not generally effective in increasing the maximum power that can be dissipated by the package in the end use environment. The variables investigated in the steady state study included die size, thermal vias and bumps, the addition of a heat sink, natural/forced convection boundary conditions, printed circuit board (PCB) heat loading, and PCB thermal conductivity. The transient portion considered die size, pulse shape and duration, and the addition of a heat sink. For relatively short duration transients (e.g. switching an inductive load), the power limit is governed by the die geometry; magnitude, shape and duration of the heating pulse; and the starting and maximum allowable temperatures of the junction.","PeriodicalId":125267,"journal":{"name":"ITherm'98. Sixth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.98CH36208)","volume":"82 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114012105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Steady state thermal characterization and junction temperature estimation of multi-chip module packages using the response surface method 基于响应面法的多芯片模块封装稳态热特性及结温估计

ITherm'98. Sixth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.98CH36208) Pub Date : 1998-05-27 DOI: 10.1109/ITHERM.1998.689522

B. Zahn

{"title":"Steady state thermal characterization and junction temperature estimation of multi-chip module packages using the response surface method","authors":"B. Zahn","doi":"10.1109/ITHERM.1998.689522","DOIUrl":"https://doi.org/10.1109/ITHERM.1998.689522","url":null,"abstract":"The steady state thermal performance of semiconductor packages has been traditionally reported through the use of a single junction-to-ambient thermal resistance constant commonly referred to as /spl theta//sub ja/. This is particularly inadequate for multi-chip modules, where several devices reside within the same package structure. This paper discusses how a central composite design of experiments can be applied to provide a more accurate thermal characterization of a multi-chip module package. The end product is a series of linear or polynomial equations which can be utilized by the customer to calculate individual device junction temperatures over a wide variation of convection cooling environments and multiple device power dissipations. A 352 plastic ball grid array package, which encompasses three individual devices, is used as an example. The paper steps through the sensitivity analysis and evaluates the accuracy of the resulting equations. This method of thermal characterization can be easily applied to single chip modules of varying power and cooling regimes, or multiple output devices where several power junctions reside within the same integrated circuit.","PeriodicalId":125267,"journal":{"name":"ITherm'98. Sixth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.98CH36208)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121860965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Thermal design of a ultra-slim notebook computer 超薄笔记本电脑的散热设计

ITherm'98. Sixth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.98CH36208) Pub Date : 1998-05-27 DOI: 10.1109/ITHERM.1998.689513

T. Kobayashi, T. Ogushi, N. Sumi, M. Fujii

引用次数: 12

Packaging for thermal management of power electronics building blocks using metal posts interconnected parallel plate structure 电力电子元件热管理用金属柱互连平行板结构的封装

ITherm'98. Sixth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.98CH36208) Pub Date : 1998-05-27 DOI: 10.1109/ITHERM.1998.689592

S. Haque, K. Xing, G. Lu, Dennis P. Nelson, D. Borojevic, F. Lee

{"title":"Packaging for thermal management of power electronics building blocks using metal posts interconnected parallel plate structure","authors":"S. Haque, K. Xing, G. Lu, Dennis P. Nelson, D. Borojevic, F. Lee","doi":"10.1109/ITHERM.1998.689592","DOIUrl":"https://doi.org/10.1109/ITHERM.1998.689592","url":null,"abstract":"We have developed a low-cost approach, termed metal posts interconnected parallel plate structure (MPIPPS), for packaging high-performance power electronics building block (PEBB) modules. PEBBs are integrated power modules consisting of power semiconductor devices, power integrated circuits, sensors and protection circuits for a wide range of power electronics applications, such as inverters for motor drives and converters for power processing equipment. This new packaging concept is based on the use of direct-bonding of copper posts, rather than wire-bonding of fine aluminium wires, to interconnect power devices. The approach requires less expensive equipment and has the potential to produce modules with superior electrical, thermal, and mechanical performance. We have demonstrated the feasibility of this approach by constructing PEBB modules consisting of two IGBTs, two power diodes, gate resistors, varistors, and a capacitor. The MPIPPS-packaged modules have been successfully tested at power levels over 6 kW.","PeriodicalId":125267,"journal":{"name":"ITherm'98. Sixth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.98CH36208)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133788396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Thermal management with additive multilayer circuitry on metal substrates 金属基板上加性多层电路的热管理

ITherm'98. Sixth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.98CH36208) Pub Date : 1998-05-27 DOI: 10.1109/ITHERM.1998.689616

G. Matijasevic, P. Gandhi, C. Gallagher, Xiao-chun Xi, L. Ha

{"title":"Thermal management with additive multilayer circuitry on metal substrates","authors":"G. Matijasevic, P. Gandhi, C. Gallagher, Xiao-chun Xi, L. Ha","doi":"10.1109/ITHERM.1998.689616","DOIUrl":"https://doi.org/10.1109/ITHERM.1998.689616","url":null,"abstract":"High density microelectronic circuit substrates have been fabricated by additive processing on metal substrates. The circuit traces and vias are fabricated using an electrically conductive paste and permanent photoimageable dielectric materials developed for microvia technologies. The conductive material is a metal-polymer composite based on transient liquid phase sintering (TLPS) technology. Bulk thermal conductivity measurements of the TLPS conductive composites show that they have similar thermal conductivity to solder. The low processing temperature (<250/spl deg/C) allows their use on Al substrates. The key attribute of the technology is its fine line multilayer circuit capability on metal substrates. To show the advantages of the additive metal substrate technology over conventional approaches, thermal dissipation has been measured by temperature mapping using emissivity compensated IR imaging. A serpentine pattern was fabricated on a variety of substrates, including Cu-clad FR-4 and Al. Thermal imaging shows the much higher power dissipating capabilities of the Al substrate. A prototype thermal test board was also fabricated and assembled with power components. The thermal dissipation of the power components was measured to be up to 75% more efficient than the baseline, a printed circuit board with thermal vias and a heat sink. The multilayer circuit technology described here was also used to fabricate a large area heat sensor which has 1600 thermocouples per square centimeter and a sensitivity of 40 mV/(W/cm/sup 2/).","PeriodicalId":125267,"journal":{"name":"ITherm'98. Sixth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.98CH36208)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114565396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Design optimization of an integrated liquid-cooled IGBT power module using CFD technique 基于CFD技术的集成液冷IGBT电源模块设计优化

ITherm'98. Sixth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.98CH36208) Pub Date : 1998-05-27 DOI: 10.1109/ITHERM.1998.689584

T. Lee

{"title":"Design optimization of an integrated liquid-cooled IGBT power module using CFD technique","authors":"T. Lee","doi":"10.1109/ITHERM.1998.689584","DOIUrl":"https://doi.org/10.1109/ITHERM.1998.689584","url":null,"abstract":"This paper presents a novel approach to optimize pin array design of an integrated, liquid-cooled, insulated gate bipolar transistor (IGBT) power module. With the aid of a computational fluid dynamics (CFD) code, the fluid field and heat transfer inside the module were analyzed, and several design options for pin arrays were examined. For IGBT die circuitry, the uniformity of temperature distribution among the dies is as critical as the magnitude of the die temperature. A noticeable variation in temperature among dies can accelerate thermal runaway and reduce device reliability. With geometrically-optimized-pin designs located both upstream and downstream of the channel, a total power dissipation of 1200 W was achieved. The maximum junction temperature was maintained at /spl sim/100/spl deg/C and the maximum variation among dies was controlled to within 1/spl deg/C. The results from this study indicated that the device junction temperatures were not only reduced in magnitude but were also equalized. In addition, the maximum power dissipation of the module was enhanced. Comparison with other direct (pool boiling) and indirect (cold plate) liquid cooling techniques was also discussed.","PeriodicalId":125267,"journal":{"name":"ITherm'98. Sixth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.98CH36208)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116444361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 66

Thermal analysis of a wirebond chip-on-board package 线键芯片板上封装的热分析

ITherm'98. Sixth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.98CH36208) Pub Date : 1998-05-27 DOI: 10.1109/ITHERM.1998.689607

Jing Pang, C. Tan

引用次数: 5