2017 IEEE International Conference on Rebooting Computing (ICRC)最新文献_第3页

Magneto-Electric Approximate Computational Circuits for Bayesian Inference 贝叶斯推理的磁电近似计算电路

2017 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2017-11-01 DOI: 10.1109/ICRC.2017.8123678

S. Kulkarni, Sachin Bhat, S. Khasanvis, C. A. Moritz

{"title":"Magneto-Electric Approximate Computational Circuits for Bayesian Inference","authors":"S. Kulkarni, Sachin Bhat, S. Khasanvis, C. A. Moritz","doi":"10.1109/ICRC.2017.8123678","DOIUrl":"https://doi.org/10.1109/ICRC.2017.8123678","url":null,"abstract":"Probabilistic graphical models like Bayesian Networks (BNs) are powerful cognitive-computing formalisms, with many similarities to human cognition. These models have a multitude of real-world applications. New emerging-technology based circuit paradigms leveraging physical equivalence e.g., operating directly on probabilities vs. introducing layers of abstraction, have shown promise in raising the performance and overall efficiency of BNs, enabling networks with millions of random variables. While previous BNs of up to 100s of nodes have been shown to require single-digit precision without affecting application outcomes, the significantly larger number of variables requires the computational precision to be scaled to correctly support BN operations. We introduce a new computational circuit fabric based on mixed-signal magneto-electric computations operating with physical equivalence and supporting probabilistic computations with a new approximate circuit style. Precision scaling impacts area at a logarithmic vs. linear scale offering a much lower power and performance cost than in prior directions. Results show 30x area reduction for a 0.001 precision vs. prior direction, while maintaining three orders of magnitude benefits vs. 100-core processor implementations.","PeriodicalId":125114,"journal":{"name":"2017 IEEE International Conference on Rebooting Computing (ICRC)","volume":"208-209 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130714133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A Comparison between Single Purpose and Flexible Neuromorphic Processor Designs 单一用途与柔性神经形态处理器设计之比较

2017 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2017-11-01 DOI: 10.1109/ICRC.2017.8123641

D. Mountain, Mark McLean, Christopher D. Krieger

引用次数: 1

On-Chip Passive Photonic Reservoir Computing with Integrated Optical Readout 集成光学读出的片上无源光子库计算

2017 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2017-11-01 DOI: 10.1109/ICRC.2017.8123673

Matthias Freiberger, A. Katumba, P. Bienstman, J. Dambre

引用次数: 14

A Bayesian Stochastic Machine for Sound Source Localization 声源定位的贝叶斯随机机

2017 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2017-11-01 DOI: 10.1109/ICRC.2017.8123681

Raphael Frisch, R. Laurent, M. Faix, Laurent Girin, L. Fesquet, A. Lux, J. Droulez, P. Bessière, E. Mazer

{"title":"A Bayesian Stochastic Machine for Sound Source Localization","authors":"Raphael Frisch, R. Laurent, M. Faix, Laurent Girin, L. Fesquet, A. Lux, J. Droulez, P. Bessière, E. Mazer","doi":"10.1109/ICRC.2017.8123681","DOIUrl":"https://doi.org/10.1109/ICRC.2017.8123681","url":null,"abstract":"Compared to conventional processors, stochastic computing architectures have strong potential to speed up computation time and to reduce power consumption. We present such an architecture, called Bayesian Machine (BM), dedicated to solving Bayesian inference problems. Given a set of noisy signals provided by low-level sensors, a BM estimates the posterior probability distribution of an unknown target information. In the present study, a BM is used to solve a sound source localization (SSL) problem: the BM computes the probability distribution of the position of a sound source given acoustic signals captured by a set of microphones. Assuming free field wave propagation (no reverberations), we express the SSL problem as the maximization of a likelihood function fed with audio features provided by the time-frequency (TF) analysis of the captured audio waves. The proposed BM uses bitwise parallel sampling to fuse the resulting multi-channel information. As the number of channels to fuse is large, the standard BM architecture encounters the so-called ``time dilution problem\" (long delays are necessary to obtain valid samples). We tackle this problem by using max-normalization of the distributions combined with a periodic re-sampling of the bit streams after processing a reasonably small subset of evidences. Finally, we compare the localization performance of the proposed machine with the results obtained using a standard version of the machine. The re-sampling leads to an impressive acceleration factor of 10³ in the computation.","PeriodicalId":125114,"journal":{"name":"2017 IEEE International Conference on Rebooting Computing (ICRC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122850744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Energy-Efficient Single-Flux-Quantum Based Neuromorphic Computing 节能单通量量子神经形态计算

2017 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2017-11-01 DOI: 10.1109/ICRC.2017.8123634

M. Schneider, C. Donnelly, S. Russek, B. Baek, M. Pufall, P. Hopkins, W. Rippard

引用次数: 12

Structure Discovery for Gene Expression Networks with Emerging Stochastic Hardware 基于新兴随机硬件的基因表达网络结构发现

2017 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2017-11-01 DOI: 10.1109/ICRC.2017.8123688

S. Kulkarni, Sachin Bhat, C. A. Moritz

{"title":"Structure Discovery for Gene Expression Networks with Emerging Stochastic Hardware","authors":"S. Kulkarni, Sachin Bhat, C. A. Moritz","doi":"10.1109/ICRC.2017.8123688","DOIUrl":"https://doi.org/10.1109/ICRC.2017.8123688","url":null,"abstract":"Gene Expression Networks (GENs) attempt to model how genetic information stored in the DNA (Genotype) results in the synthesis of proteins, and consequently, the physical traits of an organism (Phenotype). Deciphering GENs plays an important role in a wide range of applications from genetic studies of the origins of life to personalized healthcare. Probabilistic graphical models such as Bayesian Networks (BNs) are used to perform learning and inference of GENs from genetic data. Current techniques of generating BNs of GENs from data, which are mostly approximate in nature, involve searching and scoring of multiple probabilistic graphical structures. However, while search algorithms can be efficiently implemented in software, the same is not true for scoring. Scoring of probabilistic models with inherent parallelism is inefficient when performed sequentially over conventional architectures comprising of deterministic devices. In this paper, we introduce a new nanoscale hardware acceleration framework, enabling fast and efficient Bayesian inference operations, significantly accelerating the scoring aspect of the BN learning of GENs using a combination of emerging stochastic devices and CMOS technology. The stochasticity of the devices is utilized to efficiently perform approximate inference on probabilistic networks, and the circuit framework constituting these devices is designed to exploit the inherent parallelism in these models. We demonstrate approximate inference operation over a small BN. We estimate the performance benefits of five orders of magnitude in performing inference operations using this architecture over software-only approaches.","PeriodicalId":125114,"journal":{"name":"2017 IEEE International Conference on Rebooting Computing (ICRC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122471768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Spatial-Spectral Materials for High Performance Optical Processing 用于高性能光学处理的空间光谱材料

2017 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2017-11-01 DOI: 10.1109/ICRC.2017.8123674

Z. Barber, C. Harrington, K. Rupavatharam, C. Thiel, T. Jackson, P. Sellin, C. Benko, K. Merkel

引用次数: 1

A New Approach for Multi-Valued Computing Using Machine Learning 基于机器学习的多值计算新方法

2017 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2017-11-01 DOI: 10.1109/ICRC.2017.8123646

Wafi Danesh, Mostafizur Rahman

{"title":"A New Approach for Multi-Valued Computing Using Machine Learning","authors":"Wafi Danesh, Mostafizur Rahman","doi":"10.1109/ICRC.2017.8123646","DOIUrl":"https://doi.org/10.1109/ICRC.2017.8123646","url":null,"abstract":"To continue scaling in future and to meet emerging application requirements, revolutionary concepts are required not just on \"how can we find better switches to implement computers\", but also on \"how computers compute logic\". Multi-Valued Logic (MVL) provides one such opportunity, since efficient implementation of MVL can allow compact and enhanced information processing and be orders of magnitude efficient than binary CMOS. Emerging devices such as Quantum Dots, Magnetic Tunnel Junctions (MTJs), Carbon Nanotube FETs (CNTFETs), Spin Wave Devices etc., provide an avenue for hardware implementation of MVL. So far, MVL lagged behind CMOS due to (a) complexities associated with traditional logic decomposition approaches, which result in many MVL minterms, complex polynomials of order greater than two, and cumbersome decision diagrams that are difficult to implement, and (b) multi-valued data representation, processing and communication using binary switches and medium, which are inefficient. In this paper, we propose a transformative new direction for multi-valued logic decomposition (problem (a)) utilizing concepts from machine learning and nanoelectronics. In our approach, given a MVL function, we perform iterative linear regressions on all input and output combinations to derive a set of linear expressions. A visual pattern matching technique is then applied to derive selection conditions for each linear expression based on the function inputs. The set of linear expressions and corresponding selection criteria ensure that for all function inputs, correct outputs are obtained. The resulting linear expressions are hardware implementation friendly and can be implemented with simple gates and summation functions. In this paper, we show an approach to solve (b) by implementing a quaternary multiplier using our technique. Our detailed comparison with existing methods suggests huge benefits can be attained with the proposed method.","PeriodicalId":125114,"journal":{"name":"2017 IEEE International Conference on Rebooting Computing (ICRC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127226416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Securing Data Centers, Handheld Computers, and Networked Sensors against Viruses and Rootkits 保护数据中心、掌上电脑和网络传感器免受病毒和rootkit的侵害

2017 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2017-11-01 DOI: 10.1109/ICRC.2017.8123687

Earle Jennings

引用次数: 0

Advanced Packaging and Heterogeneous Integration to Reboot Computing 重新启动计算的高级封装和异构集成

2017 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2017-11-01 DOI: 10.1109/ICRC.2017.8123637

Saptadeep Pal, S. Iyer, Puneet Gupta

{"title":"Advanced Packaging and Heterogeneous Integration to Reboot Computing","authors":"Saptadeep Pal, S. Iyer, Puneet Gupta","doi":"10.1109/ICRC.2017.8123637","DOIUrl":"https://doi.org/10.1109/ICRC.2017.8123637","url":null,"abstract":"In the past several decades on-chip dimensions have scaled over 2000X, while dimensions on printed circuit board have scaled 4-5X. This modest scaling of packaging dimensions has severely limited system scaling. To address this, we have proposed a disruptive package-free integration scheme. We replace the traditional organic printed circuit board (PCB) with silicon interconnect fabric (SiIF) and replace the traditional package by directly mounting bare chiplets on to the SiIF. Fine pitch solderless copper pillar connections increase IO density by 20-80X and the inter-chiplet spacing is reduced by 10-20X. This enables highly parallel communication instead of serialized links. This achieves higher bandwidth/mm (~100X) and lower latency (~25X) and lower communication energy per bit (~200X). This integration technology allows us to challenge the conventional communication-limited architectures in a substantial way. The ability to heterogeneously integrate diverse dies with arbitrarily fine granularity, but on a wafer scale, reduces the cost of processor-memory communication energy opening new compute paradigms. In addition, the superior heat spreading properties of the SiIF compared to organic PCBs allows us to run the cores harder. The heterogeneous integration property of our scheme, allows for an intimate mingling of heterogeneous processor cores, FPGAs and memory types opening new avenues to reboot computing.","PeriodicalId":125114,"journal":{"name":"2017 IEEE International Conference on Rebooting Computing (ICRC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121311332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2