2017 IEEE International Conference on Rebooting Computing (ICRC)最新文献

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Computing Based on Material Training: Application to Binary Classification Problems 基于材料训练的计算:在二元分类问题中的应用
2017 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2017-11-01 DOI: 10.1109/ICRC.2017.8123677
E. Vissol-Gaudin, A. Kotsialos, C. Groves, C. Pearson, D. Zeze, M. Petty
{"title":"Computing Based on Material Training: Application to Binary Classification Problems","authors":"E. Vissol-Gaudin, A. Kotsialos, C. Groves, C. Pearson, D. Zeze, M. Petty","doi":"10.1109/ICRC.2017.8123677","DOIUrl":"https://doi.org/10.1109/ICRC.2017.8123677","url":null,"abstract":"Evolution-in-materio is a form of unconventional computing combining materials' training and evolutionary search algorithms. In previous work, a mixture of single-walled-carbon-nanotubes (SWCNTs) dispersed in a liquid crystal (LC) was trained so that its morphology and electrical properties were gradually changed to perform a computational task. Material-based computation is treated as an optimisation problem with a hybrid search space consisting of the voltages used for creating the electrical field and the material's infinitely possible SWCNT arrangements in LC. In this paper, we study solutions using synthetic data with a non-linear separating boundary. In addition, results for two real life datasets with partly merged classes are presented. The training process is based on a differential evolution (DE) algorithm, which subjects the SWCNT/LC material to repeated electrical charging, leading to progressive morphological and electric conductivity modifications. It is shown that the material configuration the DE algorithm converges to form a non-negligible part of the solution. Furthermore, the problem's complexity is relevant to the properties of the resulting \"physical solver\". The material structures created when training for a problem allow the retraining for a less complex one. The result is a doubly-trained material that keeps the memory of the original more complex problem. This is not the case for doubly-trained materials where initial training is for the less complex problem. The optimal electric field found by the DE algorithm is also a necessary solution component for the material's output to be interpreted as a computation.","PeriodicalId":125114,"journal":{"name":"2017 IEEE International Conference on Rebooting Computing (ICRC)","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134113541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Demonstration of a Coherent Tunable Amplifier for All-Optical Ising Machines 全光激光机相干可调谐放大器的演示
2017 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2017-11-01 DOI: 10.1109/ICRC.2017.8123671
T. Vaerenbergh, G. Mendoza, D. Kielpinski, J. Pelc, N. Tezak, R. Bose, C. Santori, R. Beausoleil
{"title":"Demonstration of a Coherent Tunable Amplifier for All-Optical Ising Machines","authors":"T. Vaerenbergh, G. Mendoza, D. Kielpinski, J. Pelc, N. Tezak, R. Bose, C. Santori, R. Beausoleil","doi":"10.1109/ICRC.2017.8123671","DOIUrl":"https://doi.org/10.1109/ICRC.2017.8123671","url":null,"abstract":"Coherent Ising machines are a type of optical accelerators that can solve different optimization tasks by encoding the problem in the connection matrix of the network. So far, experimental realizations have been limited to time multiplexed solutions, in which one nonlinear node is present in a feedback loop. In Hewlett Packard Labs, we investigate the implementation of a spatially multiplexed solution, with an array of nominally identical nonlinear nodes. As this avoids the need for a long delayline, this makes the system more suitable for integration and hence mass production. In this paper, we demonstrate a phasesensitive amplifier, a critical component in integrated circuits for this type of all-optical computing, as it allows to overcome circuit losses in the passive connection matrix of the circuit and waveguide losses in the feedback loop. The amplifier is fabricated in amorphous silicon-on- insulator and relies on thermo-optic selfheating in a ring-loaded Mach-Zehnder interferometer, although the concept is transferable to other types of nonlinearities. The effective gain is tunable by controlling the power and phase of the bias input. While we propose this amplifier in the context of all-optical integrated coherent Ising machines, this amplifier can be used in other applications where coherent amplification is required without the need to add a gain material in the fabrication flow.","PeriodicalId":125114,"journal":{"name":"2017 IEEE International Conference on Rebooting Computing (ICRC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115443719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Synchronised 4-Phase Resonant Power Clock Supply for Energy Efficient Adiabatic Logic 同步4相谐振电源时钟供应节能绝热逻辑
2017 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2017-11-01 DOI: 10.1109/ICRC.2017.8123661
Nicolas Jeanniot, G. Pillonnet, P. Nouet, N. Azémard, A. Todri
{"title":"Synchronised 4-Phase Resonant Power Clock Supply for Energy Efficient Adiabatic Logic","authors":"Nicolas Jeanniot, G. Pillonnet, P. Nouet, N. Azémard, A. Todri","doi":"10.1109/ICRC.2017.8123661","DOIUrl":"https://doi.org/10.1109/ICRC.2017.8123661","url":null,"abstract":"Adiabatic logic is an alternative architecture design style to reduce the power consumption of digital cores by using AC power supply instead of DC ones. The energy saving of the digital gates is strongly related to the efficiency of adiabatic AC power supplies. In this paper, we propose a resonant reversible power-clock supply design with four different phases. The resonance deviation between the four power-clock supplies is synchronized thanks to 12 control signals (3 controls signals per power-clock supply).We derive the energy dissipation of a 4-stage PFAL pipeline circuit supplied with the proposed resonant powerclock supply, which can dissipate up to 2.9 times less energy than a non-adiabatic CMOS pipeline.","PeriodicalId":125114,"journal":{"name":"2017 IEEE International Conference on Rebooting Computing (ICRC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129986052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Asynchronous Ballistic Reversible Computing 异步弹道可逆计算
2017 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2017-11-01 DOI: 10.1109/ICRC.2017.8123659
M. Frank
{"title":"Asynchronous Ballistic Reversible Computing","authors":"M. Frank","doi":"10.1109/ICRC.2017.8123659","DOIUrl":"https://doi.org/10.1109/ICRC.2017.8123659","url":null,"abstract":"Most existing concepts for hardware implementation of reversible computing invoke an adiabatic computing paradigm, in which individual degrees of freedom (e.g., node voltages) are synchronously transformed under the influence of externally- supplied driving signals. But distributing these \"power/clock\" signals to all gates within a design while efficiently recovering their energy is difficult. Can we reduce clocking overhead using a ballistic approach, wherein data signals self- propagating between devices drive most state transitions? Traditional concepts of ballistic computing, such as the classic Billiard-Ball Model, typically rely on a precise synchronization of interacting signals, which can fail due to exponential amplification of timing differences when signals interact. In this paper, we develop a general model of Asynchronous Ballistic Reversible Computing (ABRC) that aims to address these problems by eliminating the requirement for precise synchronization between signals. Asynchronous reversible devices in this model are isomorphic to a restricted set of Mealy finite- state machines. We explore ABRC devices having up to 3 bidirectional I/O terminals and up to 2 internal states, identifying a simple pair of such devices that comprises a computationally universal set of primitives. We also briefly discuss how ABRC might be implemented using single flux quanta in superconducting circuits.","PeriodicalId":125114,"journal":{"name":"2017 IEEE International Conference on Rebooting Computing (ICRC)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126412791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A Spike-Timing Neuromorphic Architecture 尖峰定时神经形态结构
2017 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2017-11-01 DOI: 10.1109/ICRC.2017.8123631
A. Hill, Jonathon W. Donaldson, Fred Rothganger, C. Vineyard, D. Follett, Pamela L. Follett, Michael R. Smith, Stephen J Verzi, William M. Severa, Felix Wang, J. Aimone, J. Naegle, C. James
{"title":"A Spike-Timing Neuromorphic Architecture","authors":"A. Hill, Jonathon W. Donaldson, Fred Rothganger, C. Vineyard, D. Follett, Pamela L. Follett, Michael R. Smith, Stephen J Verzi, William M. Severa, Felix Wang, J. Aimone, J. Naegle, C. James","doi":"10.1109/ICRC.2017.8123631","DOIUrl":"https://doi.org/10.1109/ICRC.2017.8123631","url":null,"abstract":"Unlike general purpose computer architectures that are comprised of complex processor cores and sequential computation, the brain is innately parallel and contains highly complex connections between computational units (neurons). Key to the architecture of the brain is a functionality enabled by the combined effect of spiking communication and sparse connectivity with unique variable efficacies and temporal latencies. Utilizing these neuroscience principles, we have developed the Spiking Temporal Processing Unit (STPU) architecture which is well-suited for areas such as pattern recognition and natural language processing. In this paper, we formally describe the STPU, implement the STPU on a field programmable gate array, and show measured performance data.","PeriodicalId":125114,"journal":{"name":"2017 IEEE International Conference on Rebooting Computing (ICRC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116776738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
An Energy-Efficient Mixed-Signal Neuron for Inherently Error-Resilient Neuromorphic Systems 固有错误弹性神经形态系统的节能混合信号神经元
2017 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2017-10-24 DOI: 10.1109/ICRC.2017.8123656
Baibhab Chatterjee, P. Panda, Shovan Maity, K. Roy, Shreyas Sen
{"title":"An Energy-Efficient Mixed-Signal Neuron for Inherently Error-Resilient Neuromorphic Systems","authors":"Baibhab Chatterjee, P. Panda, Shovan Maity, K. Roy, Shreyas Sen","doi":"10.1109/ICRC.2017.8123656","DOIUrl":"https://doi.org/10.1109/ICRC.2017.8123656","url":null,"abstract":"This work presents the design and analysis of a mixed-signal neuron (MS-N) for convolutional neural networks (CNN) and compares its performance with a digital neuron (Dig-N) in terms of operating frequency, power and noise. The circuit- level implementation of the MS-N in 65 nm CMOS technology exhibits 2-3 orders of magnitude better energy-efficiency over Dig-N for neuromorphic computing applications - especially at low frequencies due to the high leakage currents from many transistors in Dig-N. The inherent error- resiliency of CNN is exploited to handle the thermal and flicker noise of MS-N. A system-level analysis using a cohesive circuit-algorithmic framework on MNIST and CIFAR-10 datasets demonstrate an increase of 3% in worst-case classification error for MNIST when the integrated noise power in the bandwidth is ~ 1 μV².","PeriodicalId":125114,"journal":{"name":"2017 IEEE International Conference on Rebooting Computing (ICRC)","volume":"221 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132525658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Neuromorphic Adaptive Edge-Preserving Denoising Filter 神经形态自适应保边去噪滤波器
2017 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2017-09-24 DOI: 10.1109/ICRC.2017.8123644
A. Irmanova, O. Krestinskaya, A. P. James
{"title":"Neuromorphic Adaptive Edge-Preserving Denoising Filter","authors":"A. Irmanova, O. Krestinskaya, A. P. James","doi":"10.1109/ICRC.2017.8123644","DOIUrl":"https://doi.org/10.1109/ICRC.2017.8123644","url":null,"abstract":"In this paper, we present an on-sensor neuromorphic vision hardware implementation of denoising spatial filter. The mean or median spatial filters with fixed window shape are known for its denoising ability, however, have the drawback of blurring the object edges. The effect of blurring increases with increase in window size. To preserve the edge information, we propose a spatial filter that uses neurons ability to detect similar pixels and calculate the mean. The analog input differences of neighbornood pixels are converted to a chain of pulses with voltage controlled oscillator and applied as neuron inputs. When the input pulses charge the neuron to equal or greater level than its threshold, the neuron will fire, and pixels are identified as similar. The sequence of the neuron's responses for pixels is stored in the serial-in-parallel-out shift register. The outputs of shift registers are used as input to the selector switches of an averaging circuit making this an adaptive mean operation resulting in an edge preserving mean filter. System level simulation of the hardware is conducted using 150 images from Caltech database with added Gaussian noise to test the robustness of edge-preserving and denoising ability of the proposed filter. Threshold values of the hardware neuron were adjusted so that the proposed edge-preserving spatial filter achieves optimal performance in terms of PSNR and MSE, and these results outperforms that of the conventional mean and median filters.","PeriodicalId":125114,"journal":{"name":"2017 IEEE International Conference on Rebooting Computing (ICRC)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134079994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Towards On-Chip Optical FFTs for Convolutional Neural Networks 面向卷积神经网络的片上光学fft
2017 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2017-08-31 DOI: 10.1109/ICRC.2017.8123675
J. George, Hani Nejadriahi, V. Sorger
{"title":"Towards On-Chip Optical FFTs for Convolutional Neural Networks","authors":"J. George, Hani Nejadriahi, V. Sorger","doi":"10.1109/ICRC.2017.8123675","DOIUrl":"https://doi.org/10.1109/ICRC.2017.8123675","url":null,"abstract":"Convolutional neural networks have become an essential element of spatial deep learning systems. In the prevailing architecture, the convolution operation is performed with Fast Fourier Transforms (FFT) electronically in GPUs. The parallelism of GPUs provides an efficiency over CPUs, however both approaches being electronic are bound by the speed and power limits of the interconnect delay inside the circuits. Here we present a silicon photonics based architecture for convolutional neural networks that harnesses the phase property of light to perform FFTs efficiently. Our all-optical FFT is based on nested Mach-Zender Interferometers, directional couplers, and phase shifters, with backend electro-optic modulators for sampling. The FFT delay depends only on the propagation delay of the optical signal through the silicon photonics structures. Designing and analyzing the performance of a convolutional neural network deployed with our on-chip optical FFT, we find dramatic improvements by up to 10^3 when compared to state-of-the-art GPUs when exploring a compounded figure-of-merit given by power per convolution over area. At a high level, this performance is enabled by mapping the desired mathematical function, an FFT, synergistically onto hardware, in this case optical delay interferometers.","PeriodicalId":125114,"journal":{"name":"2017 IEEE International Conference on Rebooting Computing (ICRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134629911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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