{"title":"Spectral Response of Ternary Logic Netlists","authors":"M. Thornton, T. Manikas","doi":"10.1109/ISMVL.2013.52","DOIUrl":"https://doi.org/10.1109/ISMVL.2013.52","url":null,"abstract":"Past methods for computation of the spectrum of a multiple-valued logic network usually rely on first characterizing the network in terms of a switching function, secondly in mapping the function values to complex numbers, and thirdly in performing the computation resulting in the spectrum. More recent approaches use decision diagram (DD) representations but still require initial formation of a DD representing the logic network switching function before the spectrum is computed. A method is described that derives a spectral transfer function directly from a netlist representation. The spectral transfer function can then be used to compute either the logic network spectral response for a specified input, or for computation of the entire Chrestenson spectrum. This method avoids the need for representing the network as a DD before computing the spectrum and can be used to directly compute either a single spectral response, the entire netlist spectrum, or the spectrum of subcircuits contained within a netlist.","PeriodicalId":124947,"journal":{"name":"2013 IEEE 43rd International Symposium on Multiple-Valued Logic","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125277530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Comparing Performance of a Multiple-Valued Time-Based Serial Data Link with Other Serial Links","authors":"M. Rashdan, J. Haslett","doi":"10.1109/ISMVL.2013.19","DOIUrl":"https://doi.org/10.1109/ISMVL.2013.19","url":null,"abstract":"A comparison between the multiple-valued differential-time-signaling (MVDTS) link and other serial links is presented in this paper. An example of a 4-bit 1.6Gbps serial link has been designed and simulated using SerDes and differential-time-signaling (DTS) architectures. A commercial FPGA kit has been used to implement the simulated serial links and the results have been compared to the simulated results. In addition, a 6-bit 15Gbps serial link has been designed using SerDes, DTS and MVDTS links. A comparison among the three links, based on the simulated results in terms of design details and spectral content, is provided. The MVDTS shows advantages over the two other serial links, in that it concentrates the transmitted signal energy in lower bandwidth compared to the DTS and SerDes links, uses much lower input clock frequency compared to the SerDes link for the same link rate, and has better jitter characteristics.","PeriodicalId":124947,"journal":{"name":"2013 IEEE 43rd International Symposium on Multiple-Valued Logic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127042041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Laura Tague, Mathias Soeken, S. Minato, R. Drechsler
{"title":"Debugging of Reversible Circuits Using pDDs","authors":"Laura Tague, Mathias Soeken, S. Minato, R. Drechsler","doi":"10.1109/ISMVL.2013.22","DOIUrl":"https://doi.org/10.1109/ISMVL.2013.22","url":null,"abstract":"Different kinds of decision diagrams have played key roles in advancements for the synthesis of reversible circuits in the recent past. In this work, decision diagrams are used to efficiently debug reversible circuits in cases when they do not match their intentional specification. It can automatically be checked whether the faulty circuit is almost equal to a given function, i.e. it can realize the function by slightly modifying the circuit, e.g. by adding or changing a gate. For this purpose, πDDs are used which allow for a compact representation of a set of permutations.","PeriodicalId":124947,"journal":{"name":"2013 IEEE 43rd International Symposium on Multiple-Valued Logic","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131515216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. A. Mannan, K. Tanno, H. Tamura, Takako Toyama, A. Darmawansyah
{"title":"Expandable MVL Inverter Compatible with Standard CMOS Process and Its Application to MVL Hysteresis Comparator","authors":"A. A. Mannan, K. Tanno, H. Tamura, Takako Toyama, A. Darmawansyah","doi":"10.1109/ISMVL.2013.27","DOIUrl":"https://doi.org/10.1109/ISMVL.2013.27","url":null,"abstract":"In this paper, a novel voltage-mode MVL inverter is proposed. The proposed inverter consists of two circuit blocks: MVL threshold comparator and Multi-level generator, which can be implemented by standard CMOS technologies. Next, the inverted MVL hysteresis comparator is also proposed as the application of the proposed MVL inverter. The proposed MVL inverter and inverted MVL hysteresis comparator are expandable, capable to use more numbers of levels in MVL circuits. The performances of all proposed MVL circuits were evaluated through HSPICE with the set of 0.18μm CMOS process parameters. From the simulation results, we could confirm that all proposed MVL circuits work well as theory.","PeriodicalId":124947,"journal":{"name":"2013 IEEE 43rd International Symposium on Multiple-Valued Logic","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133249948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ben Schaeffer, Linh Tran, Addison Gronquist, M. Perkowski, P. Kerntopf
{"title":"Synthesis of Reversible Circuits Based on Products of Exclusive OR Sums","authors":"Ben Schaeffer, Linh Tran, Addison Gronquist, M. Perkowski, P. Kerntopf","doi":"10.1109/ISMVL.2013.54","DOIUrl":"https://doi.org/10.1109/ISMVL.2013.54","url":null,"abstract":"This paper introduces a new synthesis approach called Products of EXOR-sums (POE) and demonstrates its utility when employed in an Exclusive-Or-Sum-of-Products (ESOP) based algorithm for reversible and permutative quantum circuits restricted to single output functions. Unlike previous ESOP approaches such as EXORCISM-4 which realize functions as an EXOR-ed sum of product literals, this new algorithm realizes functions as an EXOR-ed sum of POEs (EPOE). A comparison of EXORCISM-4 and EPOE circuits shows that the latter approach often produces circuits with significantly lower quantum costs.","PeriodicalId":124947,"journal":{"name":"2013 IEEE 43rd International Symposium on Multiple-Valued Logic","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134285656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Kamiura, Tomoya Fukuda, A. Saitoh, T. Isokawa, N. Matsui, Hitoshi Tabuchi
{"title":"On Selection of Intraocular Power Formula Using Support Vector Machines and Genetic Algorithm","authors":"N. Kamiura, Tomoya Fukuda, A. Saitoh, T. Isokawa, N. Matsui, Hitoshi Tabuchi","doi":"10.1109/ISMVL.2013.44","DOIUrl":"https://doi.org/10.1109/ISMVL.2013.44","url":null,"abstract":"In this paper, selection of formulas to calculate intraocular lens (IOL) power is presented for a cataract patient, using support vector machines (SVM's) and genetic algorithm (GA). Each of the used data belongs to one of the three classes specified by names of the power formulas. The proposed method addresses the formula selection as the issue of classifying the data associated with the patient. The formulas have variables into which values of axial length and corneal refractive power are substituted, and hence each of the data has elements associated with them. Other elements probably useful in classifying the data are determined by GA. The final discrimination model is constructed by SVM learning using the above data. It consists of three coordinate spaces having two regions corresponding to two formulas out of three. Each of the spaces provides a potential solution. The formula to be used for some patient is specified by a majority of the potential solutions. The experimental results establish that the proposed method achieves the substantial percentage of concordance for the classification.","PeriodicalId":124947,"journal":{"name":"2013 IEEE 43rd International Symposium on Multiple-Valued Logic","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134372772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On Hyper Co-Clones","authors":"Jelena Colic, Hajime Machida, J. Pantović","doi":"10.1109/ISMVL.2013.42","DOIUrl":"https://doi.org/10.1109/ISMVL.2013.42","url":null,"abstract":"In this paper, we study closed sets of relations that are preserved by hyperoperations. We examine three already known Galois connections between hyperoperations and relations, and show that none of them induces a relational clone. We also introduce the notion of extended co-clone, and prove that there is a Galois connection (rPol, rInv) between extended hyperoperations on A and relations on non-void subsets of A with the property that rInv F is an extended co-clone. Moreover, we show that the three previously known classes of hyperclones can be defined by rPol.","PeriodicalId":124947,"journal":{"name":"2013 IEEE 43rd International Symposium on Multiple-Valued Logic","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125014237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Lowering Error Floors in Stochastic Decoding of LDPC Codes Based on Wire-Delay Dependent Asynchronous Updating","authors":"N. Onizawa, W. Gross, T. Hanyu, V. Gaudet","doi":"10.1109/ISMVL.2013.35","DOIUrl":"https://doi.org/10.1109/ISMVL.2013.35","url":null,"abstract":"Stochastic decoding provides ultra-low-complexity hardware for high-throughput parallel low-density parity-check (LDPC) decoders. Asynchronous stochastic decoding was pro- posed to demonstrate the possibility of low power dissipation and high throughput in stochastic decoders, but decoding might stop before convergence due to \"lock-up\", causing error floors. In this paper, we introduce wire-delay dependent asynchronous stochastic decoding to reduce the error floors. Instead of assigning the same delay to all computation nodes in the previous work, different computation delay is assigned to each computation node depending on its wire length. The variation of update timing increases switching activities to decrease the possibility of the \"lock-up\", lowering the error floors. BER performance using a regular (1024, 512) (3, 6) LDPC code is simulated based on our timing model that has computation and wire delays estimated under ASPLA 90nm CMOS technology. It is demonstrated that the proposed asynchronous decoder achieves an up to 0.25-dB gain compared with that of the synchronous and the conventional asynchronous decoders.","PeriodicalId":124947,"journal":{"name":"2013 IEEE 43rd International Symposium on Multiple-Valued Logic","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129436795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Analysis of Reversible and Quantum Finite State Machines Using Homing, Synchronizing and Distinguishing Input Sequences","authors":"M. Lukac, M. Kameyama, M. Perkowski, P. Kerntopf","doi":"10.1109/ISMVL.2013.15","DOIUrl":"https://doi.org/10.1109/ISMVL.2013.15","url":null,"abstract":"We present an analysis of the Reversible and Quantum Finite State Machines (QFSM) realized as Quantum Circuits using the three well known sequences applied in the analysis of the classical Finite State Machines (FSM). The synchronizing, the homing and the distinguishing sequences are applied to both strictly Reversible FSM (RFSM) and QFSM in order to determine the power of these new techniques in the above mentioned new models of sequential devices. In particular, care is taken to demonstrate these classical techniques on the RFSM and the one-way QFSMs. We show certain properties of the RFSM/QFSM with respect to these sequences and we show what are the restrictions and advantages.","PeriodicalId":124947,"journal":{"name":"2013 IEEE 43rd International Symposium on Multiple-Valued Logic","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122612395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design and Evaluation of a Differential Switching Gate for Low-Voltage Applications","authors":"M. Natsui, Kiyohiro Kashiuchi, T. Hanyu","doi":"10.1109/ISMVL.2013.23","DOIUrl":"https://doi.org/10.1109/ISMVL.2013.23","url":null,"abstract":"A new basic switching gate based on differential logic is proposed for implementing high-performance low-voltage VLSI. Differential switching gate operates in current domain and output voltage swing can be determined independent of supply voltage, which leads to a high frequency operation even if in a lower-supply-voltage condition. Moreover, the use of a modified pMOS load further improves the transient characteristic of the switching gate. Through an evaluation of a differential logic-based combinational circuit, a potential capability of the differential switching gate is demonstrated.","PeriodicalId":124947,"journal":{"name":"2013 IEEE 43rd International Symposium on Multiple-Valued Logic","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128360896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}