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Formal Methods in System Design最新文献

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Two SAT solvers for solving quantified Boolean formulas with an arbitrary number of quantifier alternations 两个SAT求解器，用于求解具有任意数量量词替换的量化布尔公式
IF 0.8 4区 计算机科学
Formal Methods in System Design Pub Date : 2021-08-01 DOI: 10.1007/s10703-021-00371-7
Roderick Bloem, Nicolas Braud-Santoni, Vedad Hadžić, U. Egly, Florian Lonsing, M. Seidl
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引用次数: 2
Reluplex: a calculus for reasoning about deep neural networks Reluplex:用于深层神经网络推理的微积分
IF 0.8 4区 计算机科学
Formal Methods in System Design Pub Date : 2021-07-01 DOI: 10.1007/s10703-021-00363-7
Guy Katz, Clark W. Barrett, D. Dill, Kyle D. Julian, Mykel J. Kochenderfer
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引用次数: 34
Certifying proofs for SAT-based model checking 基于SAT的模型检查的证明
IF 0.8 4区 计算机科学
Formal Methods in System Design Pub Date : 2021-06-24 DOI: 10.1007/s10703-021-00369-1
A. Griggio, Marco Roveri, Stefano Tonetta
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引用次数: 8
Information-flow control on ARM and POWER multicore processors ARM和POWER多核处理器上的信息流控制
IF 0.8 4区 计算机科学
Formal Methods in System Design Pub Date : 2021-06-08 DOI: 10.1007/s10703-021-00376-2
Graeme Smith, Nicholas Coughlin, Toby C. Murray
{"title":"Information-flow control on ARM and POWER multicore processors","authors":"Graeme Smith, Nicholas Coughlin, Toby C. Murray","doi":"10.1007/s10703-021-00376-2","DOIUrl":"https://doi.org/10.1007/s10703-021-00376-2","url":null,"abstract":"","PeriodicalId":12430,"journal":{"name":"Formal Methods in System Design","volume":"58 1","pages":"251 - 293"},"PeriodicalIF":0.8,"publicationDate":"2021-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1007/s10703-021-00376-2","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48282148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Interpolating bit-vector formulas using uninterpreted predicates and Presburger arithmetic 内插位矢量公式使用未解释的谓词和普雷斯伯格算术
IF 0.8 4区 计算机科学
Formal Methods in System Design Pub Date : 2021-05-12 DOI: 10.1007/s10703-021-00372-6
Peter Backeman, Philipp Rümmer, Aleksandar Zeljić
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引用次数: 1
Faster algorithms for quantitative verification in bounded treewidth graphs 有界树宽图中更快的定量验证算法
IF 0.8 4区 计算机科学
Formal Methods in System Design Pub Date : 2021-04-29 DOI: 10.1007/s10703-021-00373-5
K. Chatterjee, Rasmus Ibsen-Jensen, A. Pavlogiannis
{"title":"Faster algorithms for quantitative verification in bounded treewidth graphs","authors":"K. Chatterjee, Rasmus Ibsen-Jensen, A. Pavlogiannis","doi":"10.1007/s10703-021-00373-5","DOIUrl":"https://doi.org/10.1007/s10703-021-00373-5","url":null,"abstract":"","PeriodicalId":12430,"journal":{"name":"Formal Methods in System Design","volume":"57 1","pages":"401 - 428"},"PeriodicalIF":0.8,"publicationDate":"2021-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1007/s10703-021-00373-5","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48675875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Preface of the special issue on the conference on computer-aided verification 2018 2018计算机辅助验证大会特刊前言
IF 0.8 4区 计算机科学
Formal Methods in System Design Pub Date : 2021-04-28 DOI: 10.1007/s10703-021-00365-5
Hana Chockler, Georg Weissenbacher
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引用次数: 0
Rely-guarantee bound analysis of parameterized concurrent shared-memory programs 参数化并发共享内存程序的可靠保证界分析
IF 0.8 4区 计算机科学
Formal Methods in System Design Pub Date : 2021-04-06 DOI: 10.1007/s10703-021-00370-8
Thomas Pani, Georg Weissenbacher, Florian Zuleger
{"title":"Rely-guarantee bound analysis of parameterized concurrent shared-memory programs","authors":"Thomas Pani, Georg Weissenbacher, Florian Zuleger","doi":"10.1007/s10703-021-00370-8","DOIUrl":"https://doi.org/10.1007/s10703-021-00370-8","url":null,"abstract":"","PeriodicalId":12430,"journal":{"name":"Formal Methods in System Design","volume":"57 1","pages":"270 - 302"},"PeriodicalIF":0.8,"publicationDate":"2021-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1007/s10703-021-00370-8","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"52227067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
SAT modulo discrete event simulation applied to railway design capacity analysis 卫星模离散事件仿真在铁路设计能力分析中的应用
IF 0.8 4区 计算机科学
Formal Methods in System Design Pub Date : 2021-03-31 DOI: 10.1007/s10703-021-00368-2
Bjørnar Luteberget, Koen Claessen, Christian Johansen, M. Steffen
{"title":"SAT modulo discrete event simulation applied to railway design capacity analysis","authors":"Bjørnar Luteberget, Koen Claessen, Christian Johansen, M. Steffen","doi":"10.1007/s10703-021-00368-2","DOIUrl":"https://doi.org/10.1007/s10703-021-00368-2","url":null,"abstract":"","PeriodicalId":12430,"journal":{"name":"Formal Methods in System Design","volume":"57 1","pages":"211 - 245"},"PeriodicalIF":0.8,"publicationDate":"2021-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1007/s10703-021-00368-2","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44687020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Equivalence checking and intersection of deterministic timed finite state machines 确定性定时有限状态机的等价性检验与交集
IF 0.8 4区 计算机科学
Formal Methods in System Design Pub Date : 2021-03-08 DOI: 10.1007/s10703-022-00396-6
Davide Bresolin, K. El-Fakih, T. Villa, N. Yevtushenko
{"title":"Equivalence checking and intersection of deterministic timed finite state machines","authors":"Davide Bresolin, K. El-Fakih, T. Villa, N. Yevtushenko","doi":"10.1007/s10703-022-00396-6","DOIUrl":"https://doi.org/10.1007/s10703-022-00396-6","url":null,"abstract":"","PeriodicalId":12430,"journal":{"name":"Formal Methods in System Design","volume":"59 1","pages":"77 - 102"},"PeriodicalIF":0.8,"publicationDate":"2021-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44714478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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