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2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines最新文献

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Power Visualization, Analysis, and Optimization Tools for FPGAs fpga的电源可视化、分析和优化工具
2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2006-04-24 DOI: 10.1109/FCCM.2006.58
M. French, Li Wang, M. Wirthlin
{"title":"Power Visualization, Analysis, and Optimization Tools for FPGAs","authors":"M. French, Li Wang, M. Wirthlin","doi":"10.1109/FCCM.2006.58","DOIUrl":"https://doi.org/10.1109/FCCM.2006.58","url":null,"abstract":"This paper introduces the low-power intelligent tool environment (LITE), an object oriented tool set designed for power visualization, analysis, and optimization. These tools leverage an established FPGA design environment, JHDL, that allows design logic and power utilization to be displayed, analyzed, and cross-probed simultaneously at a level of abstraction close to the design entry point. Circuit logic, FPGA architecture and power information are correlated to create accurate power prediction and estimation models. These models and power analysis tools can then be used to create power optimization algorithms. Power optimization algorithm development is supported through the use of tools to query and sort circuit characteristics and drop in COTS CAD tool compliant constraints. These constraints can be used to guide the COTS placement and routing tools to optimize for power","PeriodicalId":123057,"journal":{"name":"2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126021179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
COPACOBANA A Cost-Optimized Special-Purpose Hardware for Code-Breaking COPACOBANA是一种成本优化的用于密码破译的专用硬件
2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2006-04-24 DOI: 10.1109/FCCM.2006.34
Sandeep S. Kumar, C. Paar, J. Pelzl, Gerd Pfeiffer, M. Schimmler
{"title":"COPACOBANA A Cost-Optimized Special-Purpose Hardware for Code-Breaking","authors":"Sandeep S. Kumar, C. Paar, J. Pelzl, Gerd Pfeiffer, M. Schimmler","doi":"10.1109/FCCM.2006.34","DOIUrl":"https://doi.org/10.1109/FCCM.2006.34","url":null,"abstract":"Cryptanalysis of symmetric and asymmetric ciphers is computationally extremely demanding. Since the security parameters of almost all practical crypto algorithms are chosen such that attacks with conventional computers are computationally infeasible, the only promising way to tackle existing ciphers (assuming no mathematical breakthrough) is to build special-purpose hardware. This contribution presents a special-purpose hardware labeled COPACOBANA (cost-optimized parallel code breaker), which is optimized for running crypt-analytical algorithms with low communication overhead. The price-performance ratio as primary and a cost margin of less than US$ 10,000 as secondary design goal led to a reconfigurable computer built as cluster of programmable logic devices","PeriodicalId":123057,"journal":{"name":"2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125162522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Pre-synthesis Queue Size Estimation of Streaming Data Flow Graphs 流数据流图的预合成队列大小估计
2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2006-04-24 DOI: 10.1109/FCCM.2006.59
Somsubhra Mondal, S. Memik, Nikolaos Bellas
{"title":"Pre-synthesis Queue Size Estimation of Streaming Data Flow Graphs","authors":"Somsubhra Mondal, S. Memik, Nikolaos Bellas","doi":"10.1109/FCCM.2006.59","DOIUrl":"https://doi.org/10.1109/FCCM.2006.59","url":null,"abstract":"In this paper the authors propose a pre-synthesis register queue size estimation technique for an unscheduled streaming DFG (sDFG) for pipelined synthesis. Our estimation method first designates a minimum queue size to each communication edge of the sDFG based on the ALAP value of the source node and ASAP value of the sink node of that edge. Our aim is to further refine this initial minimum queue size estimation. Our main tool is based on the likelihood estimation that the source node may actually be producing data before its ALAP time, and likewise, the sink node may actually be consuming data after its ASAP time","PeriodicalId":123057,"journal":{"name":"2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116131805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Reconfigurable Cluster-on-Chip Architecture with MPI Communication Layer 具有MPI通信层的可重构集群片上架构
2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2006-04-24 DOI: 10.1109/FCCM.2006.14
John A. Williams, Irfan Syed, Jason Wu, N. Bergmann
{"title":"A Reconfigurable Cluster-on-Chip Architecture with MPI Communication Layer","authors":"John A. Williams, Irfan Syed, Jason Wu, N. Bergmann","doi":"10.1109/FCCM.2006.14","DOIUrl":"https://doi.org/10.1109/FCCM.2006.14","url":null,"abstract":"In this paper, the authors present a reconfigurable cluster-on-chip architecture and supporting parallel programming software library based on the well-known message passing interface (MPI) standard. The intent is to allow designers to program multi-core reconfigurable systems on chip using the same or similar methodologies that yielded tremendous productivity improvements in the workstation and HPC cluster community. Additionally the architecture is designed to support native hardware processing modules to participate in the MPI network as fully-fledged peers","PeriodicalId":123057,"journal":{"name":"2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128463974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
VPN Acceleration Using Reconfigurable System-On-Chip Technology 使用可重构系统芯片技术的VPN加速
2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2006-04-24 DOI: 10.1109/FCCM.2006.72
C. Wee, P. Sutton, N. Bergmann, John A. Williams
{"title":"VPN Acceleration Using Reconfigurable System-On-Chip Technology","authors":"C. Wee, P. Sutton, N. Bergmann, John A. Williams","doi":"10.1109/FCCM.2006.72","DOIUrl":"https://doi.org/10.1109/FCCM.2006.72","url":null,"abstract":"This paper presents a network architecture that can be implemented on a reconfigurable System-on-Chip (rSoC) that will accelerate the operation of Virtual Private Networks (VPNs). With a small and efficient 3DES-CBC core coupled the flexibility of the rSoC and a network architecture that can scale as needed, this can be an effective solution to the current real world requirement for a flexible and affordable VPN platform.","PeriodicalId":123057,"journal":{"name":"2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines","volume":"520 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134432130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An FPGA Solution for Radiation Dose Calculation 一种辐射剂量计算的FPGA解决方案
2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2006-04-24 DOI: 10.1109/FCCM.2006.23
Kevin Whitton, X. Hu, Cedric X. Yu, D. Chen
{"title":"An FPGA Solution for Radiation Dose Calculation","authors":"Kevin Whitton, X. Hu, Cedric X. Yu, D. Chen","doi":"10.1109/FCCM.2006.23","DOIUrl":"https://doi.org/10.1109/FCCM.2006.23","url":null,"abstract":"Radiation dose calculation is an important step in the treatment of cancer patients requiring radiation therapy. It ensures that the physician prescribed dose agrees with the dose delivered to the patient. Current methods use software implementing either three-dimensional (3D) convolution/superposition algorithms or Monte Carlo analysis. These software methods create a bottleneck in radiation therapy. The required computation time limits both the accuracy of the calculation and the number of patients whom can be treated. This paper presents a novel FPGA implementation for radiation dose calculation. The implementation is based on the 3D convolution/superposition collapsed cone algorithm (Ahnesjo, 1989). To achieve higher accuracy and performance, the original algorithm has been modified and advanced design techniques were applied. Experimental data demonstrate that the FPGA implementation shows significant improvements over software implementation","PeriodicalId":123057,"journal":{"name":"2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132435696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A Reconfigurable Distributed Computing Fabric Exploiting Multilevel Parallelism 利用多层并行性的可重构分布式计算结构
2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2006-04-24 DOI: 10.1109/FCCM.2006.15
Charles L. Cathey, J. Bakos, D. Buell
{"title":"A Reconfigurable Distributed Computing Fabric Exploiting Multilevel Parallelism","authors":"Charles L. Cathey, J. Bakos, D. Buell","doi":"10.1109/FCCM.2006.15","DOIUrl":"https://doi.org/10.1109/FCCM.2006.15","url":null,"abstract":"This paper presents a novel reconfigurable data flow processing architecture that promises high performance by explicitly targeting both fine- and course-grained parallelism. This architecture is based on multiple FPGAs organized in a scalable direct network that is substantially more interconnect-efficient than currently used crossbar technology. In addition, we discuss several ancillary issues and propose solutions required to support this architecture and achieve maximal performance for general-purpose applications; these include supporting IP, mapping techniques, and routing policies that enable greater flexibility for architectural evolution and code portability","PeriodicalId":123057,"journal":{"name":"2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126304849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
CAD Tool for FPGAs with Embedded Hard Cores for Design Space Exploration of Future Architectures 用于未来架构设计空间探索的嵌入式硬核fpga CAD工具
2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2006-04-24 DOI: 10.1109/FCCM.2006.30
Simin Dai, E. Bozorgzadeh
{"title":"CAD Tool for FPGAs with Embedded Hard Cores for Design Space Exploration of Future Architectures","authors":"Simin Dai, E. Bozorgzadeh","doi":"10.1109/FCCM.2006.30","DOIUrl":"https://doi.org/10.1109/FCCM.2006.30","url":null,"abstract":"In this work, the goal is to develop a flexible CAD tool by which designers can explore integration of different types of embedded hard cores and interfaces in the FPGA architectures. Our tool takes a RTL design and defined embedded hard cores. The authors have modified VPR for place and route with embedded blocks. We have experimented different modules to be embedded as hard cores on a FPGA device. We also explore the FPGA routing architecture with embedded hard cores by applying uniform and non-uniform routing channels. In many cases, non-uniform channels produce more area-efficient architectures. Our results show that there is a need for a tool for better exploration of design space for FPGAs with embedded hard cores","PeriodicalId":123057,"journal":{"name":"2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116966319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Scalable Softcore Vector Processor for Biosequence Applications 用于生物序列应用的可扩展软核矢量处理器
2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2006-04-24 DOI: 10.1109/FCCM.2006.62
A. Jacob, Brandon Harris, J. Buhler, R. Chamberlain, Young-Hee Cho
{"title":"Scalable Softcore Vector Processor for Biosequence Applications","authors":"A. Jacob, Brandon Harris, J. Buhler, R. Chamberlain, Young-Hee Cho","doi":"10.1109/FCCM.2006.62","DOIUrl":"https://doi.org/10.1109/FCCM.2006.62","url":null,"abstract":"Currently available genome databases are growing exponentially in size, making it difficult for software analysis tools to keep up. A number of hardware accelerators utilizing special purpose VLSI (Blas, et al., 2005) or reconfigurable hardware (Hoang, 1993) have been proposed. However, they are inflexible; support for new applications usually requires a laborious redesign. None of these accelerators can be easily adapted to other applications that require differing hardware resources. The design philosophy of the softcore vector processor is based on two important goals: adaptability and performance. Instruction based execution allows programmable support for a large number of algorithms. The fact that different classes of applications require different subsets of hardware resources, argues for a customizable hardware design built from primitives. The second goal was to achieve programmability without sacrificing performance. The SVP was designed to perform competitively with full custom solutions available in the market","PeriodicalId":123057,"journal":{"name":"2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131084301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A Parallel Hardware Architecture for fast Gaussian Elimination over GF(2) GF(2)上快速高斯消去的并行硬件结构
2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Pub Date : 2006-04-24 DOI: 10.1109/FCCM.2006.12
A. Bogdanov, M. Mertens, C. Paar, J. Pelzl, Andy Rupp
{"title":"A Parallel Hardware Architecture for fast Gaussian Elimination over GF(2)","authors":"A. Bogdanov, M. Mertens, C. Paar, J. Pelzl, Andy Rupp","doi":"10.1109/FCCM.2006.12","DOIUrl":"https://doi.org/10.1109/FCCM.2006.12","url":null,"abstract":"This paper presents a hardware-optimized variant of the well-known Gaussian elimination over GF(2) and its highly efficient implementation. The proposed hardware architecture can solve any regular and (uniquely solvable) overdetermined linear system of equations (LSE) and is not limited to matrices of a certain structure. Besides solving LSEs, the architecture at hand can also accomplish the related problem of matrix inversion extremely fast. Its average running time for n times n binary matrices with uniformly distributed entries equals 2n (clock cycles) as opposed to about frac14n3 in software. The average running time remains very close to 2n for matrices with densities much greater or lower than 0.5. The architecture has a worst-case time complexity of O(n2) and also a space complexity of O(n2). With these characteristics the architecture is particularly suited to efficiently solve medium-sized LSEs as they for example appear in the cryptanalysis of certain stream cipher classes. Moreover, we propose a hardware-optimized algorithm for matrix-by-matrix multiplication over GF(2) which runs in linear time and quadratic space on a similar architecture. This opens up the possibility of building a more complex architecture for efficiently solving larger LSEs by means of Strassen's algorithm which could significantly improve the time complexity of algebraic attacks on various ciphers. As proof-of-concept we realized our architecture on a contemporary low-cost FPGA. The implementation for a 50 times 50 LSE can be clocked with a frequency of up to 300 MHz and computes the solution in 0.33 mus on average","PeriodicalId":123057,"journal":{"name":"2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126797912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 52
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