Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004.最新文献

Design and evaluation of a network-based architecture for cryptographic devices 基于网络的加密设备体系结构的设计与评估

Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004. Pub Date : 2004-10-18 DOI: 10.1109/ASAP.2004.1342470

Ljiljana Dilparic, D. Arvind

引用次数: 0

Switching-activity minimization on instruction-level loop for VLIW DSP applications VLIW DSP应用中指令级循环的切换活动最小化

Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004. Pub Date : 2004-10-18 DOI: 10.1109/ASAP.2004.10023

Z. Shao, Qingfeng Zhuge, Meilin Liu, Bin Xiao, E. Sha

引用次数: 1

CHARMED: a multi-objective co-synthesis framework for multi-mode embedded systems 用于多模式嵌入式系统的多目标协同合成框架

Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004. Pub Date : 2004-09-27 DOI: 10.1109/ASAP.2004.10027

V. Kianzad, S. Bhattacharyya

引用次数: 51

A low-power carry skip adder with fast saturation 具有快速饱和的低功耗进位跳跃式加法器

Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004. Pub Date : 2004-09-27 DOI: 10.1109/ASAP.2004.10038

M. Schulte, K. Chirca, J. Glossner, Haoran Wang, S. Mamidi, P. Balzola, S. Vassiliadis

{"title":"A low-power carry skip adder with fast saturation","authors":"M. Schulte, K. Chirca, J. Glossner, Haoran Wang, S. Mamidi, P. Balzola, S. Vassiliadis","doi":"10.1109/ASAP.2004.10038","DOIUrl":"https://doi.org/10.1109/ASAP.2004.10038","url":null,"abstract":"We present the design of a carry skip adder that achieves low power dissipation and high-performance operation. The carry skip adder's delay and power dissipation are reduced by dividing the adder into variable-sized blocks that balance the delay of inputs to the carry chain. This grouping reduces active power by minimizing extraneous glitches and transitions. Each block also uses highly optimized complementing carry look-ahead logic to reduce delay. Compared to previous designs, the adder architecture decreases power consumption by reducing the number of transistors, logic levels, and glitches. A 32-bit carry skip adder design that uses our approach has been implemented in 130 nm CMOS technology. At 1.2 V and 25 C, the 32-bit adder has a critical path delay of 921 ps and average power dissipation normalized to 600 MHz operation of 0.786 mW. We also present a technique to quickly perform saturating addition, which is useful in a variety of digital signal processing and multimedia applications. Our technique for fast saturation is based on techniques for carry select addition and works particularly well when the input and output operands can have different formats. A 40-bit carry skip adder that uses our technique for fast saturation has critical path delays of 1149 ps in 130 nm technology at 1.2 V and 25 C and 560 ps in 90nm technology at 1.0 V and 25 C. The 40-bit adder's average power dissipation normalized to 600 MHz operation is 0.928 mW in 130 nm technology and 0.335 mW in 90 nm technology.","PeriodicalId":120245,"journal":{"name":"Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131064883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Binary multiplication based on single electron tunneling 基于单电子隧穿的二进制倍增

Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004. Pub Date : 2004-09-27 DOI: 10.1109/ASAP.2004.10019

C. Lageweg, S. Cotofana, S. Vassiliadis

引用次数: 7

Resource constrained and speculative scheduling of an algorithm class with run-time dependent conditionals 具有运行时依赖条件的算法类的资源约束和推测调度

Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004. Pub Date : 2004-09-27 DOI: 10.1109/ASAP.2004.10029

Frank Hannig, J. Teich

引用次数: 31

Defect-tolerant molecular electronics 耐缺陷分子电子学

Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004. Pub Date : 2004-09-27 DOI: 10.1109/ASAP.2004.18

P. Kuekes

引用次数: 7

An algorithm and hardware architecture for integrated modular division and multiplication in GF(p) and GF(2/sup n/) GF(p)和GF(2/sup n/)中集成模除法和乘法的算法和硬件结构

Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004. Pub Date : 2004-09-27 DOI: 10.1109/ASAP.2004.10034

L. Tawalbeh, A. Tenca

引用次数: 22

A packet scheduling algorithm for IPSec multi-accelerator based systems 基于IPSec多加速器系统的数据包调度算法

Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004. Pub Date : 2004-09-27 DOI: 10.1109/ASAP.2004.10016

F. Castanier, A. Ferrante, V. Piuri

引用次数: 9

Detecting faults in four symmetric key block ciphers 四种对称密钥分组密码的故障检测

Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004. Pub Date : 2004-09-27 DOI: 10.1109/ASAP.2004.10035

L. Breveglieri, I. Koren, P. Maistri

引用次数: 9