{"title":"Design and evaluation of a network-based architecture for cryptographic devices","authors":"Ljiljana Dilparic, D. Arvind","doi":"10.1109/ASAP.2004.1342470","DOIUrl":null,"url":null,"abstract":"This work presents a network-based asynchronous architecture that improves the physical-level security of cryptographic devices to known side-channel attacks. This is achieved by decorrelating power consumption measurements by exploiting parallel execution and randomised data-forwarding over a network of functional units. Instructions execute in parallel and forward register values between them, thereby avoiding the register bank. A secret-sharing scheme is used in data-forwarding to remove the effect of sending critical register values through the network, which does not significantly degrade performance and has a positive effect of increasing the noise due to network activity. The simulation results show that both the security threshold and the performance are improved, and the network-based architecture is more robust to differential power analysis when compared to the asynchronous pipelined architecture.","PeriodicalId":120245,"journal":{"name":"Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004.","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2004-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASAP.2004.1342470","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This work presents a network-based asynchronous architecture that improves the physical-level security of cryptographic devices to known side-channel attacks. This is achieved by decorrelating power consumption measurements by exploiting parallel execution and randomised data-forwarding over a network of functional units. Instructions execute in parallel and forward register values between them, thereby avoiding the register bank. A secret-sharing scheme is used in data-forwarding to remove the effect of sending critical register values through the network, which does not significantly degrade performance and has a positive effect of increasing the noise due to network activity. The simulation results show that both the security threshold and the performance are improved, and the network-based architecture is more robust to differential power analysis when compared to the asynchronous pipelined architecture.