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引用次数: 22
摘要
本文提出了一种在GF(p)和GF(2/sup n/)域(统一)中集成模块化除法和乘法的算法和体系结构。该算法基于模除法的扩展二进制GCD算法和模乘法的Montgomery方法。对于除法操作,建议的算法使用计数器来跟踪两个字段元素之间的差异,这样就消除了通常昂贵且耗时的比较的需要。该架构有效地支持算法中的所有操作,并使用免进位的统一加法器来减少关键路径延迟,使该架构比其他先前提出的设计更快。给出了AMI 0.5 /spl μ m CMOS技术合成的实验结果,并与其他分频和乘法器进行了比较。
An algorithm and hardware architecture for integrated modular division and multiplication in GF(p) and GF(2/sup n/)
This work presents an algorithm and architecture that integrates modular division and multiplication in both GF(p) and GF(2/sup n/) fields (unified). The algorithm is based on the extended binary GCD algorithm for modular division and on the Montgomery's method for modular multiplication. For the division operation, the proposed algorithm uses a counter to keep track of the difference between two field elements and this way eliminate the need for comparisons which are usually expensive and time-consuming. The proposed architecture efficiently supports all the operations in the algorithm and uses carry-save unified adders for reduced critical path delay, making the proposed architecture faster than other previously proposed designs. Experimental results using synthesis for AMI 0.5 /spl mu/m CMOS technology are shown and compared with other dividers and multipliers.