2005 IEEE 7th CAS Symposium on Emerging Technologies: Circuits and Systems for 4G Mobile Wireless Communications最新文献_第2页

MMSE equalizer for MIMO-ISI channel with shortened guard period 缩短保护周期的MIMO-ISI信道的MMSE均衡器

2005 IEEE 7th CAS Symposium on Emerging Technologies: Circuits and Systems for 4G Mobile Wireless Communications Pub Date : 2005-06-23 DOI: 10.1109/EMRTW.2005.195683

M. Kwan, C. Kok

引用次数: 1

A Reconfigurable “SFMD Architecture” For a Class of Signal Processing Applications 可重构SFMD架构”用于一类信号处理应用

2005 IEEE 7th CAS Symposium on Emerging Technologies: Circuits and Systems for 4G Mobile Wireless Communications Pub Date : 2005-06-23 DOI: 10.1109/EMRTW.2005.195677

P. Sinha, A. Sinha, D. Basa

{"title":"A Reconfigurable “SFMD Architecture” For a Class of Signal Processing Applications","authors":"P. Sinha, A. Sinha, D. Basa","doi":"10.1109/EMRTW.2005.195677","DOIUrl":"https://doi.org/10.1109/EMRTW.2005.195677","url":null,"abstract":"The fastest programmable DSP processors are unable to meet the speed requirements of many advanced signal processing applications. SlMD machines have been a preferred solution in such applications because of their inherent spatial parallelism. In such machines, a control unit (CU) broadcasts simple machine instructions simultaneously to a number of processing elements (PEs) executing the same instruction on different data The performance of such architectures can be vastly enhanced if the PEs can execute at the level of signal processing function rather than low level machine instruction. This can be made possible if the PEs are so designed that they can receive and execute functional level instruction from the CU instead of simple machine level instruction. FPGAs have emerged as high performance flexible hardware for many signal processing applications but they are not optimised for any particular application. Hence, they can not offer highest possible performance at lowest silicon cost for a given signal processing algorithm. This paper addresses these issues by introducing a new reconfigurable DSP processor, \"single function multiple data (SFMD)\" which eliminates the drawbacks of conventional SIMD machines and offers a balance between flexibility, reconfiguration latency and performance","PeriodicalId":119938,"journal":{"name":"2005 IEEE 7th CAS Symposium on Emerging Technologies: Circuits and Systems for 4G Mobile Wireless Communications","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124813101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

On control vector structure for the minimal-time system design algorithm 最小时间系统设计算法的控制向量结构

2005 IEEE 7th CAS Symposium on Emerging Technologies: Circuits and Systems for 4G Mobile Wireless Communications Pub Date : 2005-06-23 DOI: 10.1109/EMRTW.2005.195685

A. Zemliak

引用次数: 0

The algorithm to optimize allocation and utilization of frequency spectrum for wireless access systems 无线接入系统频谱分配和利用的优化算法

2005 IEEE 7th CAS Symposium on Emerging Technologies: Circuits and Systems for 4G Mobile Wireless Communications Pub Date : 2005-06-23 DOI: 10.1109/EMRTW.2005.195672

V.V. Shahgildyan, M. Strelets

引用次数: 0

CMOS wavelet compression imager architecture CMOS小波压缩成像仪结构

2005 IEEE 7th CAS Symposium on Emerging Technologies: Circuits and Systems for 4G Mobile Wireless Communications Pub Date : 2005-06-23 DOI: 10.1109/EMRTW.2005.195691

A. Olyaei, R. Genov

引用次数: 9

Channel filters for microelectronic receivers of wireless systems 无线系统微电子接收机用信道滤波器

2005 IEEE 7th CAS Symposium on Emerging Technologies: Circuits and Systems for 4G Mobile Wireless Communications Pub Date : 2005-06-23 DOI: 10.1109/EMRTW.2005.195673

Alexander S. Korotkov, Dmitry V. Morozov, A. Tutyshkin, Hans Hauer

{"title":"Channel filters for microelectronic receivers of wireless systems","authors":"Alexander S. Korotkov, Dmitry V. Morozov, A. Tutyshkin, Hans Hauer","doi":"10.1109/EMRTW.2005.195673","DOIUrl":"https://doi.org/10.1109/EMRTW.2005.195673","url":null,"abstract":"A short overview of receiver architectures and low-pass filter specifications for wireless systems is reported. Two design procedures of low-pass filters for communication system are discussed. A CMOS transconductance-capacitor (G/sub m/-C) filter with enhanced linearity is presented as the first one. The proposed design is based on a transconductance amplifier with enhanced linearity. For the elimination of the amplifier harmonic level the compensation principle is used. The device was realized as a balanced fifth-order 1 MHz low-pass Bessel filter in 0.35 /spl mu/m CMOS process. The filter operates with a low supply voltage of +2.5 Volt. Its power consumption is 8.25 mW, the input referred RMS noise is 120 /spl mu/V (0.01 + 2 MHz), and HD3 (1 V/sub P-to-P/ @ 1 MHz) is -54 dB. Alternatively a new approach to the design of high-frequency filters with low power consumption is presented. The idea is to use current mode and voltage mode active elements with enhanced frequency range. These elements are second generation current conveyors and voltage buffers, those are used to implement integrators. The filter is realized as a switched-capacitor circuit based on an integrator chain with multi feedback loops. As an example a CMOS switched-capacitor filter with 1 MHz cut-off frequency is presented. The device was realized as an unbalanced fifth-order low-pass Chebyshev filter in 03 /spl mu/m CMOS process. The filter operates with supply voltage varying from +2.5 V to +3 V. Depending on the supply voltage its power consumption is from 3 mW to 10 mW, the input referred RMS noise is 1.9 mV (0.02 + 2 MHz @ +3 V), and HD3 (2 V/sub P-to-P/ @ 900 kHz @ +3 V) is -54 dB.","PeriodicalId":119938,"journal":{"name":"2005 IEEE 7th CAS Symposium on Emerging Technologies: Circuits and Systems for 4G Mobile Wireless Communications","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124081269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Using Floquet eigenvectors in the design of electronic oscillators 利用Floquet特征向量设计电子振荡器

2005 IEEE 7th CAS Symposium on Emerging Technologies: Circuits and Systems for 4G Mobile Wireless Communications Pub Date : 2005-06-23 DOI: 10.1109/EMRTW.2005.195690

A. Carbone, Angelo Brambilla, Fabrizio Palma

引用次数: 7

Eigenfilter based blind channel estimator 基于特征滤波器的盲信道估计

2005 IEEE 7th CAS Symposium on Emerging Technologies: Circuits and Systems for 4G Mobile Wireless Communications Pub Date : 2005-06-23 DOI: 10.1109/EMRTW.2005.195682

C. Fung, C. Kok

引用次数: 0

Optimization of the downlink frame length in adaptive systems 自适应系统中下行帧长度的优化

2005 IEEE 7th CAS Symposium on Emerging Technologies: Circuits and Systems for 4G Mobile Wireless Communications Pub Date : 2005-06-23 DOI: 10.1109/EMRTW.2005.195678

R. Trifonov

引用次数: 0

Reconfigurable front-end architectures and A/D converters for flexible wireless transceivers for 4G radios 可重构的前端架构和A/D转换器，用于4G无线电的灵活无线收发器

2005 IEEE 7th CAS Symposium on Emerging Technologies: Circuits and Systems for 4G Mobile Wireless Communications Pub Date : 2005-06-23 DOI: 10.1109/EMRTW.2005.195670

G. Gielen, E. Goris

{"title":"Reconfigurable front-end architectures and A/D converters for flexible wireless transceivers for 4G radios","authors":"G. Gielen, E. Goris","doi":"10.1109/EMRTW.2005.195670","DOIUrl":"https://doi.org/10.1109/EMRTW.2005.195670","url":null,"abstract":"Flexibility is a key feature in 4G telecom systems, where there is a demand for reconfigurable transceivers that can cope with multiple standards (cellular, WLAN, Bluetooth, etc.). Additionally, these transceivers should adapt to the environment (presence of received blockers or not, status of battery power levels, etc.) to minimize power consumption and optimize performance according to the needs of the customer and the desired quality of service. In addition, flexibility is required to cut the development time and cost to implement a new future standard into the 4G system. All this calls for a digitally controlled front-end architecture (\"software-defined radio\") with reconfigurable RF and analog baseband blocks controlled through digital programmable software. This poses serious challenges to the design of such reconfigurable yet power-efficient RF/analog blocks. For the analog-to-digital converters in the receiver, this comes down to designing a power- and area-efficient reconfigurable converter with variable bandwidth and dynamic range. The general requirements for such converters in 4G systems is described. This is then illustrated with the design of a reconfigurable continuous-time /spl Delta//spl Sigma/A/D converter with a pipelined multi-bit quantizer and 1-bit feedback. The chip has been realized in a 0.18 /spl mu/m CMOS technology. It has 3 different modes (20 MHz BW/58 dB SNDR, 4 MHz BW/60 dB SNDR, 0.2 MHz BW/70 dB SNDR). The chip has an active area of 0.9 mm/sup 2/ and the power consumption for the most demanding mode (20 MHz/58 dB) is 37 mW.","PeriodicalId":119938,"journal":{"name":"2005 IEEE 7th CAS Symposium on Emerging Technologies: Circuits and Systems for 4G Mobile Wireless Communications","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133953146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 43