Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair最新文献_第9页

Timing influenced general-cell genetic floorplanner 时间影响了一般细胞遗传地板规划器

Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair Pub Date : 1995-08-01 DOI: 10.1109/ASPDAC.1995.486214

S. M. Sait, H. Youssef, S. Tanvir, M. Benten

引用次数: 8

BIST with negligible aliasing through random cover circuits 通过随机覆盖电路具有可忽略的混叠的BIST

Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair Pub Date : 1995-08-01 DOI: 10.1109/ASPDAC.1995.486227

T. Bogue, H. Jürgensen, M. Gössel

引用次数: 2

Performance driven multiple-source bus synthesis using buffer insertion 性能驱动的多源总线合成使用缓冲区插入

Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair Pub Date : 1995-08-01 DOI: 10.1109/ASPDAC.1995.486234

Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin

引用次数: 0

Assessing the feasibility of interface designs before their implementation 在实现接口设计之前评估其可行性

Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair Pub Date : 1995-08-01 DOI: 10.1109/ASPDAC.1995.486216

M. Escalante, N. Dimopoulos

引用次数: 1

An efficient logic/circuit mixed-mode simulator for analysis of power supply voltage fluctuation 一种用于分析电源电压波动的高效逻辑/电路混合模式模拟器

Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair Pub Date : 1995-08-01 DOI: 10.1109/ASPDAC.1995.486247

M. Miyama, G. Yokomizo, M. Iwabuchi, M. Kinoshita

引用次数: 1

Pin assignment and routing on a single-layer pin grid array 单层引脚网格阵列上的引脚分配和路由

Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair Pub Date : 1995-08-01 DOI: 10.1109/ASPDAC.1995.486224

Man-Fai Yu, W. Dai

引用次数: 33

A new k-way partitioning approach for multiple types of FPGAs 多类型fpga的一种新的k-way划分方法

Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair Pub Date : 1995-08-01 DOI: 10.1109/ASPDAC.1995.486239

B. M. Riess, H.A. Giselbrecht, B. Wurth

引用次数: 4

A new system partitioning method under performance and physical constraints for multi-chip modules 基于性能和物理约束的多芯片模块系统分区新方法

Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair Pub Date : 1995-08-01 DOI: 10.1109/ASPDAC.1995.486212

Y. Katsura, T. Koide, S. Wakabayashi, N. Yoshida

{"title":"A new system partitioning method under performance and physical constraints for multi-chip modules","authors":"Y. Katsura, T. Koide, S. Wakabayashi, N. Yoshida","doi":"10.1109/ASPDAC.1995.486212","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486212","url":null,"abstract":"In this paper, we propose a new and the first MCM system partitioning method considering chip-to-chip delays, chip areas and I/O pins constraints. The proposed method consists of two steps, a clustering step considering the three constraints and an iterative improvement step with mathematical programming. In the first step, we apply two clustering algorithms considering the three constraints and reduce the size of the large MCM system partitioning problem so as to get a solution within a practical computation time. Next, it generates an initial partitioning with 0-1 integer linear programming (ILP) so as to minimize the total wire length. Since there may exist constraint violations in the initial solution, in the second step, we formulate the partitioning problem as a LP problem selecting a maximal independent set and improve it until the total number of cuts is not decreased and the three constraints are satisfied. We also showed that the number of the timing constraints can be reduced by deleting redundant timing constraints. Experimental results showed that the proposed method is able to produce partitions satisfying the three constraints and improves the number of cuts by a 27% on an average and a 30% in maximum over the conventional method [15] considering only two constrains.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125018103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A CSIC implementation with POCSAG decoder and microcontroller for paging applications 一个带有POCSAG解码器和分页应用微控制器的CSIC实现

Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair Pub Date : 1995-08-01 DOI: 10.1109/ASPDAC.1995.486210

J. Y. Lim, G. Kim, O. I.-S., J. Cho, Y. Kim, H. Kim

{"title":"A CSIC implementation with POCSAG decoder and microcontroller for paging applications","authors":"J. Y. Lim, G. Kim, O. I.-S., J. Cho, Y. Kim, H. Kim","doi":"10.1109/ASPDAC.1995.486210","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486210","url":null,"abstract":"This paper presents a CSIC (Customer Specification Integrated Circuit) implementation, which includes a 512/1200/2400 bps POCSAG decoder, PDI2400 and MC68HC05 changed by PANTECH. It can receive all the data with the rate of 512/1200/2400 bps of a single clock of 76.8 KHz. It is designed to have maximum 2 own frames for service enhancement. To improve receiver quality, a preamble detection considering frequency tolerance and a SCW (Synchronization Code Word) detection at every 4 bit is suggested. Also we consider an error correction of address and message up to 2 bits. Furthermore, it is possible with proposed PF (Preamble Frequency) error to achieve a battery life increase due to the turn-off of RF circuits when the preamble signal is detected with noises. The chip is designed using VHDL code from PDI2400 micro-architecture level. It is verified with VHDL simulation software of PowerView. Its logic diagrams are synthesized with VHDL synthesis software of PowerView. Proposed decoder and MC68HC05 CPU of MOTOROLA are integrated with about 88000 transistors by using 1.0 /spl mu/m HCMOS process and named MC68HC05PD6. It is proved that the wrong detection numbers of preamble of noises are significantly reduced in the pager system that uses our chip through the real field test. The system receiving performance is improved by 20% of average, compared with other existing systems.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128098405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Search space reduction in high level synthesis by use of an initial circuit 用初始电路减少高级合成中的搜索空间

Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair Pub Date : 1995-08-01 DOI: 10.1109/ASPDAC.1995.486358

A. Masuda, Hiroshi Imai, J.P. Hansen, M. Sekine

引用次数: 0