A new k-way partitioning approach for multiple types of FPGAs

Abstract

This paper considers the problem of partitioning a large, technology mapped circuit onto multiple FPGA devices of a specified device library. We propose an iterative three-step approach applying an analytical embedding technique, initial partitioning, and a k-way ratio cut improvement procedure. We successfully partitioned the ACM/SIGDA XILINX FPGA Benchmark circuits obtaining feasible design solutions with lower total dollar costs than previous methods. Moreover, our approach simultaneously assigns the FPGAs to physical locations on the FPGA board.