MICRO 24最新文献

On reconfigurable on-chip data caches 关于可重构的片上数据缓存

MICRO 24 Pub Date : 1991-09-01 DOI: 10.1145/123465.123504

F. Dahlgren, P. Stenström

引用次数: 15

An instruction-level performance analysis of the Multiflow TRACE 14/300 Multiflow TRACE 14/300的指令级性能分析

MICRO 24 Pub Date : 1991-09-01 DOI: 10.1145/123465.123468

M. Schuette, John Paul Shen

引用次数: 8

Software pipelining for transport-triggered architectures 用于传输触发架构的软件流水线

MICRO 24 Pub Date : 1991-09-01 DOI: 10.1145/123465.123479

J. Hoogerbrugge, H. Corporaal, Hans M. Mulder

{"title":"Software pipelining for transport-triggered architectures","authors":"J. Hoogerbrugge, H. Corporaal, Hans M. Mulder","doi":"10.1145/123465.123479","DOIUrl":"https://doi.org/10.1145/123465.123479","url":null,"abstract":"This paper discusses software pipelining for a new class of architectures that we call transport-triggered. These architectures reduce the interconnection requirements between function units. They also exhibit code scheduling possibilities which are not available in traditional operation-triggered architectures. In addition the scheduling freedom is extended by the use of so-called hybridpipelined function utits. In order to exploit this tleedom, existing scheduling techniques need to be extended. We present a software pipelirtirtg technique, based on Lam’s algorithm, which exploits the potential of !mnsport-triggered architectures. Performance results are presented for several benchmak loops. Depending on the available transport capacity, MFLOP rates may increase significantly as compared to scheduling without the ex~a degrees of freedom. As stated in [5] transport-triggered MOVE architectures have extra irtstxuction scheduling degrees of tkeedom. This paper investigates if and how those extra degrees influence the software pipelining iteration initiation interval. It therefore adapts the existing algorithms for software pipelining as developed by Lam [2]. It is shown that transport-triggering may lead to a significant reduction of the iteration initiation interval and therefore to an increase of the MIPS and/or MFLOPS rate. The remainder of this paper starts with an introduction of the MOVE class of architectures; it clari6es the idea of transporttriggered architectures. Section 3 formulates the software pipelining problem and its algorithmic solution for trrmsport-triggered architectures. Section 4 describes the architecture characteristics and benchmarks used for the measurements. In order to research the influence of the extra scheduling freedom, the algorithm has been applied to the benchmarks under dfierent scheduling disciplines. The next section (5) compares and analysis the measurements. Finally section 6 gives severaf conclusions and indicates further research to be done.","PeriodicalId":118572,"journal":{"name":"MICRO 24","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122412714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Data access microarchitectures for superscalar processors with compiler-assisted data prefetching 具有编译器辅助数据预取的超标量处理器的数据访问微体系结构

MICRO 24 Pub Date : 1991-09-01 DOI: 10.1145/123465.123478

William Y. Chen, S. Mahlke, P. Chang, Wen-mei W. Hwu

引用次数: 110

An analysis of the information content of address reference streams 地址参考流的信息内容分析

MICRO 24 Pub Date : 1991-09-01 DOI: 10.1145/123465.123470

J. Becker, A. Park, M. Farrens

引用次数: 16

Executing loops on a fine-grained MIMD architecture 在细粒度的MIMD架构上执行循环

MICRO 24 Pub Date : 1991-09-01 DOI: 10.1145/123465.123505

Sunah Lee, Rajiv Gupta

引用次数: 8

The effect of real data cache behavior on the performance of a microarchitecture that supports dynamic scheduling 真实数据缓存行为对支持动态调度的微架构性能的影响

MICRO 24 Pub Date : 1991-09-01 DOI: 10.1145/123465.123472

M. Butler, Y. Patt

引用次数: 10

A quantitative analysis of locality in dataflow programs 数据流程序中局部性的定量分析

MICRO 24 Pub Date : 1991-09-01 DOI: 10.1145/123465.123469

W. M. Miller, W. Najjar, A. Böhm

引用次数: 13

Register/ file/ cache microarchitecture study using VHDL 用VHDL研究寄存器/文件/缓存微体系结构

MICRO 24 Pub Date : 1991-09-01 DOI: 10.1145/123465.123510

Samarina Makhdoom, D. Tabak, R. Auletta

{"title":"Register/ file/ cache microarchitecture study using VHDL","authors":"Samarina Makhdoom, D. Tabak, R. Auletta","doi":"10.1145/123465.123510","DOIUrl":"https://doi.org/10.1145/123465.123510","url":null,"abstract":"The influence on the processor performance comparing the CPU register file size to on-chip cache size, in a RISC-type microprocessor is investigated using VHDL modeling. The Intel 80860(or i860) was selected as a model for this study. The Linpack benchmark was used as an example for generating performance estimates. The i860 micmarchitecture was modeled and simulated using VHDL., The i860 performance executing the Linpack benchmark was tested while modifying the size of its floating point register file (actual size: 32 32-bit, or 16 64-bit registers). The model was compiled and simulated using the Intermetrics version 3.0 VHDL toolset on a Sun-3 workstation. An instruction classification scheme, called the generic model, was developed in the course of this study. It allows rapid characterization of applications by modeling them by the distribution of instructions and their relevant properties without the need to fully specify the corresponding code or target processor architecture. The results clearly indicate a signitlcant increase in performance while executing the selected benchmark when the register file size is doubled. Further increases in the register file size result in modest increases in performance. The study also shows that in order to achieve the same performance improvement by increasing only the cache size one would have to increase the cache by more than an order of magnitude, considerably exceeding current limitations of VLSI technology.","PeriodicalId":118572,"journal":{"name":"MICRO 24","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122210165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Viewing instruction set design as an optimization problem 将指令集设计视为优化问题

MICRO 24 Pub Date : 1991-09-01 DOI: 10.1145/123465.123497

Bruce K. Holmer, A. Despain

引用次数: 23