The effect of real data cache behavior on the performance of a microarchitecture that supports dynamic scheduling

Abstract

Recent studies have demonstrated that significant parallelism exists in stigle instruoticm streams and can be exploited if the microarchitecture is equipped to take advantage of it. These studies, -however, have assumed optimistic memory systems, including 100 percent data cache hit rates and multiple independent cache ports. ‘There has been legitimate concern that when the optimistic memory systems are ~eplaced with realistic memory systems, much of the increase in performance will be lost. In this study we extend our previous work to investigate the effects of realistic cache characteristics on performance. We model the execution of three integer benchmarks and two floating point benchmarks from the SPEC suite for a series of machine configurations and cache models. For moderate-sized, direct mapped caches, interleaved to provide the statistical bandwidth required, we have found performance of between 2.4 and 4.6 instructions per cycle, and degradation of between 1 and 17 percent over the ideal memory system.