Register/ file/ cache microarchitecture study using VHDL

The influence on the processor performance comparing the CPU register file size to on-chip cache size, in a RISC-type microprocessor is investigated using VHDL modeling. The Intel 80860(or i860) was selected as a model for this study. The Linpack benchmark was used as an example for generating performance estimates. The i860 micmarchitecture was modeled and simulated using VHDL., The i860 performance executing the Linpack benchmark was tested while modifying the size of its floating point register file (actual size: 32 32-bit, or 16 64-bit registers). The model was compiled and simulated using the Intermetrics version 3.0 VHDL toolset on a Sun-3 workstation. An instruction classification scheme, called the generic model, was developed in the course of this study. It allows rapid characterization of applications by modeling them by the distribution of instructions and their relevant properties without the need to fully specify the corresponding code or target processor architecture. The results clearly indicate a signitlcant increase in performance while executing the selected benchmark when the register file size is doubled. Further increases in the register file size result in modest increases in performance. The study also shows that in order to achieve the same performance improvement by increasing only the cache size one would have to increase the cache by more than an order of magnitude, considerably exceeding current limitations of VLSI technology.