2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)最新文献

{"title":"Study of 0.6mil silver alloy wire in challenging bonding processes","authors":"Jie Wu, J. Yang, O. Yauw, I. Qin, T. Rockey, B. Chylak","doi":"10.1109/EPTC.2014.7028420","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028420","url":null,"abstract":"With competitive price and superior electrical/thermal conductivity and mechanical properties, more and more IC package industries have adopted copper (Cu) and palladium coated copper (PdCu) wires as the alternative to gold (Au) wire in the past decade. However, the high hardness and the excessive ultrasonic energy and bonding motions required during bonding of Cu wire limit its usage in areas such as memory packages and sensitive devices that are prone to damages on the pads and under-layer dielectrics. Silver (Ag) and Ag-alloy wires emerge as other alternatives since they have similar properties like wire hardness, elongation and breaking load at room temperature as Au wire while having a more competitive price. Process capability of ultra-fine (0.6mil) Ag-alloy wire, including free air balls (FAB) and bonding capability on aluminum (Al) die pads were first investigated. Factors affecting the FAB performance were studied and optimum settings were recommended. Comparison of bonding responses between Au, PdCu and Ag-alloy wires on challenging scenarios, such as overhang dies and die-to-die bonding, were also included in the study. Benchmarked Au process, Ag-alloy wire possesses great portability and wide first bond process window. Ag-alloy wire also demonstrates good bonding capability and loop shape control on challenging applications, such as overhang die and long die-to-die applications. However, further optimization of Ag-alloy process is still necessary to overcome its constrains, such as higher hardness and higher energy required during bonding of Ag-alloy wire.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131326958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Functionalised copper nanoparticles as catalysts for electroless plating","authors":"R. Litchfield, J. Graves, M. Sugden, D. Hutt, A. Cobley","doi":"10.1109/EPTC.2014.7028381","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028381","url":null,"abstract":"Electroless copper plating of insulating substrates, such as printed circuit boards, typically requires the pre-deposition of a catalyst layer onto the surface to initiate the chemical reactions. Pd/Sn based catalysts are widely used, but carry a high cost and in many cases require specialist pre-treatment of the substrate to achieve good adhesion. In this work, functionalised copper nanoparticles have been investigated as alternative catalysts for electroless deposition. Commercially available copper nanoparticles were functionalised with different organic molecules and their functionalisation was confirmed with X-ray photoelectron spectroscopy. The ability of these particles to act as a catalyst was demonstrated, however their effectiveness was found to depend on the nature of the organic molecules that were used in the functionalisation. Furthermore, significant variability was found between batches of samples in both the particle dispersion and attachment to the substrate surface, which affected the reproducibility of the coverage and adhesion of the subsequent electroless plating, for which further work is required to understand these effects.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133373330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Interfacial microstructure and shear strength of Sn-Ag-Cu based composite solders on Cu and Au/Ni metallized Cu substrates","authors":"Tama Fouzder, Y. Chan, Daniel K. Chan","doi":"10.1109/EPTC.2014.7028281","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028281","url":null,"abstract":"Nano-sized, non-reacting, non-coarsening CeO2 particles with a density close to that of solder alloy were incorporated into Sn-3.0wt%Ag-0.5wt%Cu solder paste. The interfacial microstructure and shear strength of Au/Ni metallized Cu substrates were investigated, as a function of aging time, at various temperatures. After solid state aging at low temperature, an island-shaped Cu6Sn5 intermetallic compound (IMC) layer was found to be adhered at the interfaces of the Cu/Sn-Ag-Cu solder systems. However, after a prolonged aging, a very thin, firmly adhering Cu3Sn IMC layer was observed between the Cu6Sn5 IMC layer and the Cu substrate. On the other hand, a scallop-shaped (Cu, Ni)-Sn IMC layer was found at the interfaces of the Sn-Ag-Cu based solder-Au/Ni metallized Cu substrates. As the solid-state aging time and temperature increase, the thicknesses of the IMC layers also remarkably increased. In the solder ball region of both systems, a fine microstructure of Ag3Sn and Cu6Sn5 IMC particles appeared in the β-Sn matrix. However, the growth behavior of the IMC layers of composite solders doped with CeO2 nanoparticles was inhibited, due to an accumulation of surface-active CeO2 nanoparticles at the grain boundary or in the IMC layers. In addition, the composite solder joints doped with CeO2 nanoparticles had higher shear strengths than that of the plain Sn-Ag-Cu solder joints, due to a well-controlled fine IMC particles and uniformly distributed CeO2 nanoparticles.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124353205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Tunable 3D TSV-based inductor for integrated sensors","authors":"Bruce C. Kim, Saikat Mondal, Seok-Ho Noh","doi":"10.1109/EPTC.2014.7028419","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028419","url":null,"abstract":"This paper describes the design and analysis of 3D through-silicon-via (TSV) inductors for integrated sensor applications. On-chip inductors are an integral part of small foot-print RF and analog chips. In an effort to further reduce foot-print, there have been numerous proposals of 3D TSV inductors. However, these inductors do not maintain higher quality factors due to the lossy silicon substrates through which the TSV must pass. We have designed and simulated a new structure to reduce losses through silicon substrates. Our novel structure tunes the inductors using TSV arrays for low-noise amplifiers. Through our simulation results, we were able to maintain a Q factor of approximately 5 on TSV-based inductors with excellent inductor values.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"133 6‐8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120839014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Development of fluxless bonding using deposited Gold-indium multi-layer composite for heterogeneous silicon micro-cooler stacking","authors":"B. L. Lau, Yong Han, H. Zhang, L. Zhang, X. Zhang","doi":"10.1109/EPTC.2014.7028275","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028275","url":null,"abstract":"In this paper, Gold-indium fluxless eutectic bonding at short process time has been successfully developed for stacking multi-layers and heterogeneous structure of silicon micro-cooler. This paper introduces gold-indium eutectic bonding process which uses deposited thin and multilayer composites directly onto the silicon surfaces which to be bonded. The parameters DOE (design of experiment) study was carried out to develop thermal compression bonding process conditions as tabulated in Table 1. These eutectic bonds are examined using shear test, Scanning Electron Microscope (SEM) and Energy Dispersive X-ray Spectroscopy (EDX). This shear test results is compared with eutectic AuSn which is best known as hard solders, good fatigue-resistance and mechanical properties. Nearly void-free bonds are achieved and confirmed by cross-sectional SEM and X-ray scanning. A pre-clean process steps is required to ensure sufficient wetting and good adhesion for this fluxless process. Furthermore, a thermal cycling test and Scanning Acoustic Microscope (SAM) analysis will be carried out to evaluate the failure mode, reliability of solder joint and the bonded structure.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128614026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Comparison of aluminum post etch cleaning on MEMS structures using formulated organic solvent cleaners","authors":"Lee Hou Jang Steven, V. Bliznetsov, D. Wei, Tham Dexian, S. Wickramanayaka","doi":"10.1109/EPTC.2014.7028269","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028269","url":null,"abstract":"The formulated organic solvent cleaners for aluminum (Al) post etch residues removal have been available on the market for many years. They are used in large quantities in the fabrication of integrated circuits with aluminum interconnects. However, the effectiveness of these chemistries on the aluminum MEMS structures is less well known. In this study, we compared the effectiveness of four different formulated organic solvent chemistries for Al post etch residues removal for certain types of aluminum MEMS structures. The four different formulated solvent clean chemistries evaluated in this study were ST250 from Advanced Technology Materials Incorporated (ATMI), NE14 and ACT690S from Air Products (AP), and EKC265 from DuPont. Both ST250 and NE14 were implemented in a single wafer cleaner as they are typically used in a single wafer cleaning environment. ACT690S and EKC265 were implemented in a tank on a wet bench as they were formulated to work in total immersion environment. Short loop wafers of Al MEMS structures of several microns in sizes were etched in a DPS (Decoupled Plasma Source) metal etch chamber using Cl2/BCl3 plasma followed by H2O-based plasma photoresist strip in an ASP (Advanced Strip and Passivation) chamber on the Centura etch platform. These wafers were then cleaned in one of the four different solvent chemistries for comparison. We found that each organic solvent cleaner has its own advantages and disadvantages in cleaning efficiency, cost, as well as the post etch metal corrosion. For each and every organic solvent cleaner, the process conditions during cleaning must be optimized in order to achieve the best results for residues removal and corrosion prevention.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128694426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and implementation of two different RF SiPs for micro base station","authors":"Yi He, Fengman Liu, Peng Wu, Fengze Hou, Jun Li, Jie Pan, D. Shangguan, Liqiang Cao","doi":"10.1109/EPTC.2014.7028293","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028293","url":null,"abstract":"Today a range of wireless communication products have the requirement of achieving a higher integration level. In this paper, we propose two RF SiPs based on a RF prototype board for micro base station. The two RF SiPs integrate a complete 700-2600MHz RF system that includes transmitter, receiver, and feedback module, ADC/DAC and clock module. RF SiP 1 consists of two multilayer organic substrates, which are vertically stacked by using Ball BGA interconnections. RF SiP 2 uses flexible substrate as the interconnections between the top and the bottom substrates. Compared with the original RF part on the prototype board (20cm×25cm), the size of the two RF SiPs is 5.25m×5.25cm, almost reducing system area 20 times. By comparison, the flexible substrate on RF SiP 2 provides better transmission quality of input RF signals and RF SiP 2 shares better thermal performance. Besides, the RF SiP 1 uses more conventional processes and has the potential to be fabricated with a lower cost.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125778335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Bondability and challenges of Cu ultra-fine-wire bonding","authors":"S. Sutiono, Zhang Xi, T. C. Wei, Don Syth An, M. Sarangapani, Louie Huang, Jason Hung, F. Lin","doi":"10.1109/EPTC.2014.7028261","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028261","url":null,"abstract":"Cu wire bonding has matured much over the years with improvements made not only to the Cu bonding process and optimization methodologies from bonder manufacturers, but also on capillaries and Cu wire itself. It is also part of the roadmap of many assembly houses to include ultra-fine-pitch(UFP) Cu wire applications. In this paper, various Cu wire types including coated Cu going down to as fine as 0.5mil diameter size is evaluated and compared in terms of Free-Air-Ball(FAB), 2nd bond performance in a customized QFP leadframe, 1st bond performance in a customized BGA substrate and extreme looping conditions at high and ultra-low loop are studied too. Challenges faced in Cu ultra-fine-wire(UFW) application will also be discussed. Improvement process through wire bonding parameters and making use of wire characteristics will also be covered. As wire diameter gets smaller, energy that is required to melt wire to form FAB also gets lower. Range of energy input in term of EFO Current and Firing Time also get smaller, and might be more sensitive towards noises from surrounding. Shorter Firing Time might also means less time to form concentric sphere before freezing. EFO firing approach gets more critical in this sense. Unlike gold wire that is malleable, copper wire is harder and hence does not deformed as easily. Limited by smaller capillary tip in UFP, 2nd bond contact area at UFW bonding also gets smaller. 2nd bond approach with segmented bonding was used to enhance the 2nd bond contact in this evaluation. UFP application with bond pad pitch down to as small as 30um has been reported in gold wire, however due to Cu FAB's harder nature, presence of Al splash in 1st bond posed a greater challenge in achieving this pitch with similar wire size made with Cu. Ease of bondability of CuPd has created a tendency to run CuPd wire as plug and playable wire to existing bare Cu wires. However difference observed in bonding response of CuPd from bare Cu means that slight fine tuning in looping such as the kink location might still be required.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126151898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Highly efficient packaging processes by reactive multilayer materials for die-attach in power electronic applications","authors":"M. Mueller, J. Franke","doi":"10.1109/EPTC.2014.7028295","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028295","url":null,"abstract":"In the field of power electronics, assembly and interconnection technologies play an important role for the design of modules and systems. The applied packaging technologies largely determine the electrical, thermal, and mechanical properties of the final module. In addition to conventional solder technology upcoming technologies like sintering, transient liquid phase soldering or adhesive bonding are interesting methods for the realization of the semiconductor die attach. However, all these technologies imply a costly and time-consuming process chain. An innovative alternative for die attach is represented by reactive multilayer foils, which are a class of nano-engineered materials, to realize the interconnection to the substrate. By applying reactive multilayers for interconnection of electronic components on circuit carriers there is an immense potential to shorten and simplify the process chain of assembly significantly. For example, solder paste printing processes and time-consuming reflow soldering or sintering processes can be completely eliminated. The aim is to realize the application process highly efficient with standard equipment. Therefore a completely integrated placement process is provided. However, an adequately qualification of the reactive multilayer foil as interconnection medium is necessary. From there the mechanical properties of the resulting joints are characterized in this paper.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125378373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Study of electromigration behavior of Cu pillar with micro bump on fine pitch chip-to-substrate interconnect","authors":"Hsiao Hsiang Yao, A. Trigg, C. T. Chong","doi":"10.1109/EPTC.2014.7028278","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028278","url":null,"abstract":"Current-induced failures in fine pitch Sn micro bump with Cu pillar have been investigated under a current density of 3.2×104 A/cm2 and temperature of 150°C. This process takes place in 2000 hours of electromigration test. Intermetallic compound formation, kirkendall effect, and crack contributed to this failure. There are two stages of failure mechanism for Cu pillar with micro-bump during current stressing. In first stage, the whole Sn solder was transformed into intermetallic compound and kirkendall voids were formed at the interface between the Cu pillar and Cu3Sn intermetallic compound. In second stage, the Kirkendall voids coalesced into larger porosities then formed continue crack by current stressing, led to leading bump resistance increased.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121968955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}