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Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786)最新文献

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Compilation-based software performance estimation for system level design 基于编译的系统级设计软件性能评估
Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786) Pub Date : 2000-11-08 DOI: 10.1109/HLDVT.2000.889579
M. Lazarescu, Jwahar R. Bammi, Edwin A. Harcourt, L. Lavagno, M. Lajolo
{"title":"Compilation-based software performance estimation for system level design","authors":"M. Lazarescu, Jwahar R. Bammi, Edwin A. Harcourt, L. Lavagno, M. Lajolo","doi":"10.1109/HLDVT.2000.889579","DOIUrl":"https://doi.org/10.1109/HLDVT.2000.889579","url":null,"abstract":"The paper addresses embedded software performance estimation. Known approaches use either behavioral simulation with timing annotations, or a clock cycle-accurate model of instruction execution (e.g., an instruction set simulator). We propose a hybrid approach, that features both the high simulation speed and flexibility from the former approach and the awareness of compilation optimizations and processor features of the latter. The key idea is to translate the assembler generated by a target compiler to an \"assembler-level\", functionally equivalent, C code. This code, annotated with timing and other execution related informations, is used as a very precise, yet fast, software simulation model. The approach is used in Cadence VCC, a system-level design environment. We report a comparison of several known approaches, the description of the new methodology, and experimental results, that show the effectiveness of the proposed method. We also propose several improvements.","PeriodicalId":113229,"journal":{"name":"Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786)","volume":"291 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117317009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
On choosing test criteria for behavioral level hardware design verification 行为级硬件设计验证测试标准的选择
Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786) Pub Date : 2000-11-08 DOI: 10.1109/HLDVT.2000.889572
A. Andrews, Tom Chen, J. Kok, C. Anderson, A. Read, A. Hajjar
{"title":"On choosing test criteria for behavioral level hardware design verification","authors":"A. Andrews, Tom Chen, J. Kok, C. Anderson, A. Read, A. Hajjar","doi":"10.1109/HLDVT.2000.889572","DOIUrl":"https://doi.org/10.1109/HLDVT.2000.889572","url":null,"abstract":"This paper proposes criteria for the verification of behavioral designs for hardware written in VHDL. The criteria are analogous to testing criteria for software, but were adapted to the specific needs and constructs of hardware designs written in VHDL. We examine the potential value of these criteria with respect to desirable properties for evaluation criteria that were originally developed for software. Then we apply the VHDL criteria to several design examples with varying complexities to demonstrate their practical usefulness. Although, applying software testing techniques to hardware design at the behavioral level is not new, this work, to the best of our knowledge, is the first attempt to analyze the approach from the theoretical point of view and to lay the groundwork for achieving error-free design at the behavioral level.","PeriodicalId":113229,"journal":{"name":"Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133892736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Silicon debug of a co-processor array for video applications 用于视频应用的协处理器阵列的硅调试
Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786) Pub Date : 2000-11-08 DOI: 10.1109/HLDVT.2000.889558
B. Vermeulen, Gert-Jan van Rootselaar
{"title":"Silicon debug of a co-processor array for video applications","authors":"B. Vermeulen, Gert-Jan van Rootselaar","doi":"10.1109/HLDVT.2000.889558","DOIUrl":"https://doi.org/10.1109/HLDVT.2000.889558","url":null,"abstract":"For today's multi-million transistor ICs, existing design verification techniques cannot guarantee that first silicon is designed error free. Because of this reality, there is a need for a good debug methodology. This paper describes the application of a generic silicon debug methodology to a modular video-processing chip called co-processor array (CPA). The debug hardware, which was added to the design, and the supporting debugger software are described. The application of the added debug functionality and its effectiveness during first silicon bring-up are also presented.","PeriodicalId":113229,"journal":{"name":"Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115895693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
High level fault simulation: experiments and results on ITC'99 benchmarks 高层次故障模拟:在ITC'99基准上的实验和结果
Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786) Pub Date : 2000-11-08 DOI: 10.1109/HLDVT.2000.889571
D. Federici, P. Bisgambiglia, J. Santucci
{"title":"High level fault simulation: experiments and results on ITC'99 benchmarks","authors":"D. Federici, P. Bisgambiglia, J. Santucci","doi":"10.1109/HLDVT.2000.889571","DOIUrl":"https://doi.org/10.1109/HLDVT.2000.889571","url":null,"abstract":"In this paper we present our approach for performing Behavioral Fault Simulation (BFS). This approach involves three main steps (i) the definition of an internal modeling of behavioral descriptions, and the determination of a fault model; (ii) the definition of a fault simulation technique; (iii) the implementation of this technique. Finally, this paper deals with experiments conducted on ITC'99 benchmarks in order to validate a VHDL behavioral fault simulator (BFS). The effectiveness of the BFS software is clearly demonstrated through the obtained results.","PeriodicalId":113229,"journal":{"name":"Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123688139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Compositional verification of an ATM switch module using interface recognizer/suppliers (IRS) 使用接口识别器/供应商(IRS)的ATM交换模块的组成验证
Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786) Pub Date : 2000-11-08 DOI: 10.1109/HLDVT.2000.889562
M. Jahanpour, E. Cerny
{"title":"Compositional verification of an ATM switch module using interface recognizer/suppliers (IRS)","authors":"M. Jahanpour, E. Cerny","doi":"10.1109/HLDVT.2000.889562","DOIUrl":"https://doi.org/10.1109/HLDVT.2000.889562","url":null,"abstract":"We propose an approach to compositional verification of complex systems based on the interactions at the interfaces of the components. Interactions at an interface are first recognized by a finite automaton called interface recognizer/supplier (IRS). Programming IRS as supplier of the interactions allows us to simulate inter-actions of one side of the interface while model checking the other side. We formulate the composition rule and illustrate the method on an ATM switch module.","PeriodicalId":113229,"journal":{"name":"Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786)","volume":"48 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130680259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
An RT-level fault model with high gate level correlation 具有高门电平相关性的rt级故障模型
Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786) Pub Date : 2000-11-08 DOI: 10.1109/HLDVT.2000.889551
Fulvio Corno, G. Cumani, M. Reorda, Giovanni Squillero
{"title":"An RT-level fault model with high gate level correlation","authors":"Fulvio Corno, G. Cumani, M. Reorda, Giovanni Squillero","doi":"10.1109/HLDVT.2000.889551","DOIUrl":"https://doi.org/10.1109/HLDVT.2000.889551","url":null,"abstract":"With the advent of new RT-level design and test flows, new tools are needed to migrate at the RT-level the activities of fault simulation testability analysis, and test pattern generation. This paper focuses on fault simulation at the RT-level, and aims at exploiting the capabilities of VHDL simulators to compute faulty responses. The simulator was implemented as a phototypical tool, and experimental results show that simulation of a faulty circuit is no more costly than simulation of the original circuit. The reliability of the fault coverage figures computed at the RT-level is increased thanks to an analysis of inherent VHDL redundancies, and by foreseeing classical synthesis optimizations. A set of \"rules\" is used to compute a fault list that exhibits good correlation with stuck-at faults.","PeriodicalId":113229,"journal":{"name":"Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117174212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
Functional verification of an embedded network component by co-simulation with a real network 通过与真实网络的联合仿真验证嵌入式网络组件的功能
Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786) Pub Date : 2000-11-08 DOI: 10.1109/HLDVT.2000.889561
R. Pasko, R. Cmar, P. Schaumont, S. Vernalde
{"title":"Functional verification of an embedded network component by co-simulation with a real network","authors":"R. Pasko, R. Cmar, P. Schaumont, S. Vernalde","doi":"10.1109/HLDVT.2000.889561","DOIUrl":"https://doi.org/10.1109/HLDVT.2000.889561","url":null,"abstract":"In this paper, we propose a technique for verification of the functionality of a hardware networking component by including an existing real-world network into the simulation loop. As a consequence, there is no need for a high-level network model to create the system simulation. Instead, third party hardware/software can be used for the crosschecking of the design's functionality. The technique is most suitable for C/C++ based design methodologies which can directly access the operating system (OS) network interface functions. Because of that, the integration of a real network into the simulation loop can be straightforward. We demonstrate the method on verification of a Hypertext Transfer Protocol (HTTP) hardware implementation used in a design of an embedded web-camera with direct Internet connectivity.","PeriodicalId":113229,"journal":{"name":"Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129128917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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