{"title":"Scale Invariant Feature Transform Based Image Matching and Registration","authors":"H. Kher, V. Thakar","doi":"10.1109/ICSIP.2014.12","DOIUrl":"https://doi.org/10.1109/ICSIP.2014.12","url":null,"abstract":"This paper presents Image matching and registration method that is invariant to scale, rotation, translation and illumination changes. The method is named as Scale Invariant Feature Transform (SIFT). This algorithm will detect and describe image features such as contours, points, corners etc. SIFT descriptors are the characteristic signature of the feature. The features calculated from the image to be registered should be distinctive and then it can be matched. It can be useful in object recognition, image mosaicing, 3 D reconstruction and video tracking. The simulation results shows that this algorithm works well in all types of cases having scale and rotation difference, it also register the object having occlusion and clutter background.","PeriodicalId":111591,"journal":{"name":"2014 Fifth International Conference on Signal and Image Processing","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133036374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Power-Delay Optimized 32 Bit Radix-4, Sparse-4 Prefix Adder","authors":"N. Poornima, V. S. K. Bhaaskaran","doi":"10.1109/ICSIP.2014.38","DOIUrl":"https://doi.org/10.1109/ICSIP.2014.38","url":null,"abstract":"Addition is a vital operation in all data paths. The power dissipation and speed performance remain the primary factors that identify the choice of adders. To achieve the desired energy efficiency or lower power dissipation, the selection of the particular adder topology plays a major role. The operating speed of adder or the circuit latency of adder can be minimized by the use of architectures such as Parallel Prefix Adders (PPAs). This paper presents a radix-4, 32-bit Parallel Prefix Adder with a sparseness of 4. The work involves the structural realization and implementation of a 32-bit adder using radix-4 and comparison with a radix-2 32-bit adder for the power, delay, power-delay-product (PDP) and the number of computational nodes. Simulation results reveal that the radix-4 32-bit Parallel Prefix Adder realizes minimum PDP. The effects of introducing the radix-4 and sparseness on power and delay parameters of the adder structure are analyzed. Cadence EDA tool is used for the schematic implementation of the adders and simulations have been performed using 180nm bulk CMOS technology.","PeriodicalId":111591,"journal":{"name":"2014 Fifth International Conference on Signal and Image Processing","volume":"37 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120816426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Shape Based Copy Move Forgery Detection Using Level Set Approach","authors":"K. Sudhakar, V. Sandeep, S. Kulkarni","doi":"10.1109/ICSIP.2014.40","DOIUrl":"https://doi.org/10.1109/ICSIP.2014.40","url":null,"abstract":"This paper proposes a new method to Detect Copy Move Forgery using shape signatures derived from distance map. The method is simple, fast, robust, efficient as compared to traditional approaches and is invariant to scale, rotation and aspect ratio.","PeriodicalId":111591,"journal":{"name":"2014 Fifth International Conference on Signal and Image Processing","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116032749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Low Power Square and Cube Architectures Using Vedic Sutras","authors":"V. Kunchigi, L. Kulkarni, S. Kulkarni","doi":"10.1109/ICSIP.2014.62","DOIUrl":"https://doi.org/10.1109/ICSIP.2014.62","url":null,"abstract":"In this paper low power square and cube architectures are proposed using Vedic sutras. Low power and less area square and cube architectures uses Dwandwa yoga Duplex combination properties of Urdhva Tiryagbhyam sutra and Anurupyena sutra of Vedic mathematics. Simulation results for 8-bit square and 8-bit cube shows that proposed architectures lowers the total power consumption by 45% and area by 63% when compared to the conventional architecture. Also the reduction in power consumption increases with the increase in bit width. Comparison is made between conventional and Vedic method implementations of square and cube architecture. Implementation results show a significant improvement in terms of area, power and delay. Proposed square and cube architectures can be used for high speed and low power applications. Synthesis is done on Xilinx FPGA Device using, Xilinx Family: Spartan 3E, Speed Grade: -4. Propagation delay of the proposed 8-bit square is 4ns and area consumed in terms of slices is 22 and for 8-bit cube propogation delay is 7.72ns and area consumed in terms of slices is 58. Dynamic power estimation for square and cube are 13mW and 16mW respectively.","PeriodicalId":111591,"journal":{"name":"2014 Fifth International Conference on Signal and Image Processing","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123609233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Karthik, M. Kumar, Sunil Rao, Channabasava Nucchha, Subhash S. Kulkarni
{"title":"Novel Signatures for Gait Analysis Using Level Sets","authors":"K. Karthik, M. Kumar, Sunil Rao, Channabasava Nucchha, Subhash S. Kulkarni","doi":"10.1109/ICSIP.2014.44","DOIUrl":"https://doi.org/10.1109/ICSIP.2014.44","url":null,"abstract":"Gait analysis has gained prominence towards detecting suspicious activity in public area which is generally kept under surveillance. In this paper we present the results of recognizing a person based on his gait movement. Novel signatures were built through distance mapped level set contour based on boundary and skeletal information. Gait video sequence experimented upon is silhouette corresponding to 16 subjects with 50 frames per subject. Results were found to be encouraging at first level where signatures have been compared with available subjects' gait video. The robustness is tested with morphological distortions on the query image. The subject has been found to be detected with reasonable acceptance.","PeriodicalId":111591,"journal":{"name":"2014 Fifth International Conference on Signal and Image Processing","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122906190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Classification of Ancient Epigraphs into Different Periods Using Random Forests","authors":"Soumya A, G. Hemantha Kumar","doi":"10.1109/ICSIP.2014.33","DOIUrl":"https://doi.org/10.1109/ICSIP.2014.33","url":null,"abstract":"Epigraphists, who identify the ancient inscriptions, reconstruct, translate, draw conclusions about the writings, and classify their uses according to dates, are decreasing in number and also because of the fact that repetitive tasks can be exhausting for humans and prone to errors there is a need arising for the automation of these kinds of tasks. It is observed that the characters of a script have evolved over years and transformed to the current form. The purpose of this work is to estimate the period of an epigraph which is the initial step towards automating the task of reading and deciphering inscriptions. The proposed system considers a reconstructed grayscale image of an epigraph pertaining to ancient Kannada script as its input, which is binarized using Otsu's method and then segmented to characters using Connected Component analysis. Normalized Central Moments and Zernike Moments are extracted from the segmented characters and used as the feature vectors for classification. Random Forest (RF) is used as the classifier, which is an ensemble of classification trees, and each tree votes for a class and the output class is the majority of the votes which determines the era of the input epigraph. The system developed is used to classify ancient Kannada epigraphs belonging to the period of any of these dynasties: Ashoka, Satavahana, Kadamba, Chalukya, Rastrakuta and Hoysala. The system showed good results when tested on 110 Kannada epigraph images from different eras. An analysis of the prediction rate of the epigraphs was carried out and obtained a rate of 85% using RF classifier.","PeriodicalId":111591,"journal":{"name":"2014 Fifth International Conference on Signal and Image Processing","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134159801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Desai, Kavita V. Horadi, P. Navaneet, B. Niriksha, V. Siddeshvar
{"title":"User Intervention Based Detection & Removal of Cracks from Digitized Paintings","authors":"S. Desai, Kavita V. Horadi, P. Navaneet, B. Niriksha, V. Siddeshvar","doi":"10.1109/ICSIP.2014.7","DOIUrl":"https://doi.org/10.1109/ICSIP.2014.7","url":null,"abstract":"An user intervention based advanced technique for the detection and elimination of cracks in digitized paintings and images is proposed in this paper. Usually cracks degrade the quality of painting as well as authenticity of painting becomes questionable. In the proposed method the cracks are detected by thresholding the result of the morphological top-hat transform. Further, misidentified cracks are detected either by involving user intervention or by using a semi-automatic procedure based on region growing technique. Finally, crack interpolation also called crack filling is performed using order statistics filters so as to restore the cracked image. The true positive rate and false positive rate are used to evaluate the performance of the proposed technique. We collected 2000 paintings & images classified as cracked and uncracked online digital art database for experimental purpose. The result shows achievement of true positive rate of about 98.3% at the rate of 0.1 false positive per image. This is because of providing user intervention during module called identifying mis-identified cracks.","PeriodicalId":111591,"journal":{"name":"2014 Fifth International Conference on Signal and Image Processing","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131958534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Performance Evaluation of Various Feature Extraction Techniques with Special Reference to Hand Gesture Recognition","authors":"Anjali R. Patil, S. Subbaraman","doi":"10.1109/ICSIP.2014.43","DOIUrl":"https://doi.org/10.1109/ICSIP.2014.43","url":null,"abstract":"Extraction of significant and dominant features from possibly large set of database is a crucial task. The Performance of feature extraction technique depends on the dimensions of generated features and reconstruction. In this paper we provide a comparative study of different feature extraction techniques like Discrete Cosine Transform (DCT), Discrete Wavelet Transform (DWT), Principle Component Analysis (PCA), Local Binary Pattern (LBP), DCT+Gabor, DWT+ Gabor etc. and each technique is compared with each other based on Sebastian Marcel static hand postures database[24] consisting of six postures. We have used Neural Network to compare the performances of feature extraction techniques based on Recognition Accuracy (RA), False Acceptance Rate (FAR), False Recognition Rate (FRR) and also dimensions. We found that fusion of LBP and Gabor, DWT and Gabor provides good results.","PeriodicalId":111591,"journal":{"name":"2014 Fifth International Conference on Signal and Image Processing","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130292689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Vehicle Speed Detection Using Corner Detection","authors":"KV KiranKumar, Pallavi Chandrakant, Santosh Kumar, KJ Kushal","doi":"10.1109/ICSIP.2014.46","DOIUrl":"https://doi.org/10.1109/ICSIP.2014.46","url":null,"abstract":"Vehicle speed detection is used to estimate the velocity of the moving vehicle using image and video processing techniques. Without any camera calibrations video is captured and analyzed for speed in real time. By employing frame subtraction and masking techniques, moving vehicles are segmented out. Speed is calculated using the time taken between frames and corner detected object traversed in that frames. Finally frame masking is used to differentiate between one or more vehicles. With an average error of +/-2 km/h speed detection was achieved for different video sequences.","PeriodicalId":111591,"journal":{"name":"2014 Fifth International Conference on Signal and Image Processing","volume":"125 12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124668591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design of a Low Error Fixed-Width Radix-8 Booth Multiplier","authors":"Saroja S. Bhusare, V. Bhaskaran","doi":"10.1109/ICSIP.2014.39","DOIUrl":"https://doi.org/10.1109/ICSIP.2014.39","url":null,"abstract":"In many multimedia and digital signal processing systems, fixed-width multipliers are used where a fixed format is desirable and a tolerable level of loss in accuracy is permitted. This paper proposes the design of a low error fixed-width radix-8 Booth multiplier which produces an n-bit product with two n-bit inputs. The truncation of the 2n product bits to n bits is achieved by removing about half the adder cells that are required to add the partial products. However, in order to keep the truncation error to a minimum, error compensation biases are obtained and applied to the inputs of the retained adder cells. In this proposed technique, the number of partial products is reduced to n/3 and also the number of adder cells is reduced by 50% compared with the full-width multiplier with an additional overhead of one full adder for compensation biasing. Simulation results reveal that a significant amount of error reduction is achieved with this technique. Standard EDA design environment using 180nm technology has been employed. Validation has further been made in comparison against the modified Booth fixed-width multiplier architecture.","PeriodicalId":111591,"journal":{"name":"2014 Fifth International Conference on Signal and Image Processing","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114975016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}