Low Power Square and Cube Architectures Using Vedic Sutras

Abstract

In this paper low power square and cube architectures are proposed using Vedic sutras. Low power and less area square and cube architectures uses Dwandwa yoga Duplex combination properties of Urdhva Tiryagbhyam sutra and Anurupyena sutra of Vedic mathematics. Simulation results for 8-bit square and 8-bit cube shows that proposed architectures lowers the total power consumption by 45% and area by 63% when compared to the conventional architecture. Also the reduction in power consumption increases with the increase in bit width. Comparison is made between conventional and Vedic method implementations of square and cube architecture. Implementation results show a significant improvement in terms of area, power and delay. Proposed square and cube architectures can be used for high speed and low power applications. Synthesis is done on Xilinx FPGA Device using, Xilinx Family: Spartan 3E, Speed Grade: -4. Propagation delay of the proposed 8-bit square is 4ns and area consumed in terms of slices is 22 and for 8-bit cube propogation delay is 7.72ns and area consumed in terms of slices is 58. Dynamic power estimation for square and cube are 13mW and 16mW respectively.