2008 International Conference on Electronic Design最新文献_第5页

Decimal multiplication using compact BCD multiplier 十进制乘法使用紧凑的BCD乘法器

2008 International Conference on Electronic Design Pub Date : 2008-12-01 DOI: 10.1109/ICED.2008.4786744

R. K. James, T. Shahana, K. Jacob, S. Sasi

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引用次数: 38

Compact fractal boundary microstrip antenna for RF applications 射频应用的紧凑分形边界微带天线

2008 International Conference on Electronic Design Pub Date : 2008-12-01 DOI: 10.1109/ICED.2008.4786715

P. N. Rao, N. Sarma

引用次数: 0

A Novel on chip LDO voltage regulator in 180nm 一种新颖的180nm片上LDO稳压器

2008 International Conference on Electronic Design Pub Date : 2008-12-01 DOI: 10.1109/ICED.2008.4786685

P. Rao, K. Krishnaprasad

引用次数: 5

Structure design challenge in Nano-CMOS device 纳米cmos器件的结构设计挑战

2008 International Conference on Electronic Design Pub Date : 2008-12-01 DOI: 10.1109/ICED.2008.4786729

R. Sanudin, M. Morsin, M. S. Sulong

引用次数: 0

A new approach for identifying fiber fault and detecting failure location 一种光纤故障识别和故障定位的新方法

2008 International Conference on Electronic Design Pub Date : 2008-12-01 DOI: 10.1109/ICED.2008.4786636

M. Ab-Rahman, N. Chuan, A. Premadi, K. Jumari

引用次数: 1

Methods of measurement of LTCC metallization thickness LTCC金属化厚度的测量方法

2008 International Conference on Electronic Design Pub Date : 2008-12-01 DOI: 10.1109/ICED.2008.4786684

L. S. Khiang, N. Ahmad, M. Isa, R. Alias

引用次数: 0

ON chip LDO voltage regulator with improved transient response in 180nm 改进180nm瞬态响应的ON片LDO稳压器

2008 International Conference on Electronic Design Pub Date : 2008-12-01 DOI: 10.1109/ICED.2008.4786743

P. Rao, K. K. Krishna Prasad

引用次数: 3

FPGA implementation of isolated digit recognition system using modified back propagation algorithm 基于改进反向传播算法的孤立数字识别系统的FPGA实现

2008 International Conference on Electronic Design Pub Date : 2008-12-01 DOI: 10.1109/ICED.2008.4786712

V. Amudha, B. Venkataramani, J. Manikandan

{"title":"FPGA implementation of isolated digit recognition system using modified back propagation algorithm","authors":"V. Amudha, B. Venkataramani, J. Manikandan","doi":"10.1109/ICED.2008.4786712","DOIUrl":"https://doi.org/10.1109/ICED.2008.4786712","url":null,"abstract":"In this paper, the details of implementation of an isolated digit recognition system using NiosII soft-core processor are presented. Mel Frequency Cepstral Coefficients (MFCC) is used for feature extraction, multi layer perceptron (MLP) is used for classification and self organized feature map (SOFM) is employed for dimensionality reduction of features. Using TIDIGITS speech data base, various MLP architectures are studied and it is found that the recognition accuracy of 100% is obtained with the least computational complexity using single layer MLP with 10 hidden nodes. MLP is trained using both BP and modified BP algorithms and it is observed that MBP is 2.62 times faster than BP with 100% recognition accuracy. The digit recognition system is implemented on Altera CycloneII FPGA using hardware/software partitioning and the following observations are made: implementation of radix-4 FFT and remaining blocks for the calculation of MFCC using universal CORDIC processor as hardware/software partitioning is dasia10psila times faster compared to the complete software implementation on NiosII processor. The hardware accelerator for the NIOSII processor for implementation of MLP increases the recognition speed by a factor of 278. The technique proposed in this paper is also applicable for other soft-core processor such as Microblaze and Picoblaze.","PeriodicalId":103889,"journal":{"name":"2008 International Conference on Electronic Design","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124072226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Development of efficient adaptive noise canceller using low complexity filter banks 采用低复杂度滤波器组的高效自适应消噪器的研制

2008 International Conference on Electronic Design Pub Date : 2008-12-01 DOI: 10.1109/ICED.2008.4786742

A.O. Abid Noor, S. Samad, A. Hussain

引用次数: 2

A low power CMOS voltage reference circuit with subthreshold MOSFETs 具有亚阈值mosfet的低功耗CMOS电压参考电路

2008 International Conference on Electronic Design Pub Date : 2008-12-01 DOI: 10.1109/ICED.2008.4786728

S. Ramasamy, B. Venkataramani, P. Meenatchisundaram

引用次数: 0