Circuits, Systems and Signal Processing最新文献_第4页

Design and Analysis of a Power-Efficient Dynamic Comparator with an Improved Transconductance in Ultra-low Power SAR ADC Applications 在超低功耗 SAR ADC 应用中设计和分析具有改进电感的高能效动态比较器

IF 2.3 3区工程技术

Circuits, Systems and Signal Processing Pub Date : 2024-08-13 DOI: 10.1007/s00034-024-02818-8

Zahra Mehrabi Moghadam, Mohammad Reza Salehi, Salman Roudgar Nashta, Ebrahim Abiri

{"title":"Design and Analysis of a Power-Efficient Dynamic Comparator with an Improved Transconductance in Ultra-low Power SAR ADC Applications","authors":"Zahra Mehrabi Moghadam, Mohammad Reza Salehi, Salman Roudgar Nashta, Ebrahim Abiri","doi":"10.1007/s00034-024-02818-8","DOIUrl":"https://doi.org/10.1007/s00034-024-02818-8","url":null,"abstract":"This paper presents an ultra-low power comparator with minimum delay and low offset, used in successive approximation register analog-to-digital converters (SAR ADCs) for biomedical system-on-chips (SoCs). To reduce the power consumption, the proposed comparator is designed with a minimum supply voltage in the sub-threshold region. Additionally, intermediate switches are utilized in the design to serve two purposes: 1) breaking the connection between the latch and preamplifier parts during the pre-charge phase to reduce power consumption, 2) reducing the parasitic resistance of the discharge path during the evaluation phase to enhance effective transconductance of the latch (({g}_{meff,latch})). Furthermore, the proposed design incorporates, two transistors as auxiliary paths to increase the speed of discharging in the latching process. Overall, the proposed design aims to achieve a low power and high-performance comparator simulated at a frequency of 50 kHz using TSMC 65nm CMOS technology. The post-layout simulation results show that the proposed structure enjoyed from an ultra-low power consumption of 141.4 pW as well as excellent delay and offset with 357 ns and 3.32 mV values, respectively. The occupied area of the designed layout for the proposed comparator is 106.8 μm2 allowed us to embed it in multi-channel recording system on chips (SoCs). The Figure of Merit (FoM) of the proposed comparator is 0.000463 fVW/Hz. Moreover, the proposed comparator has been validated by using it in successive approximation conversion algorithm with a sampling frequency of 1 kS/s.","PeriodicalId":10227,"journal":{"name":"Circuits, Systems and Signal Processing","volume":"8 1","pages":""},"PeriodicalIF":2.3,"publicationDate":"2024-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142212284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Exploring Discrete Haar Wavelet and Cosine Transforms for Accuracy-and Energy-Quality VLSI Watermarking Systems Design 探索用于精度和能量质量 VLSI 水印系统设计的离散哈小波和余弦变换

IF 2.3 3区工程技术

Circuits, Systems and Signal Processing Pub Date : 2024-08-13 DOI: 10.1007/s00034-024-02802-2

Morgana M. A. da Rosa, Eduardo A. C. da Costa, Rafael Soares, Sergio Bampi

{"title":"Exploring Discrete Haar Wavelet and Cosine Transforms for Accuracy-and Energy-Quality VLSI Watermarking Systems Design","authors":"Morgana M. A. da Rosa, Eduardo A. C. da Costa, Rafael Soares, Sergio Bampi","doi":"10.1007/s00034-024-02802-2","DOIUrl":"https://doi.org/10.1007/s00034-024-02802-2","url":null,"abstract":"Digital watermarking conceals data within host images to safeguard against unauthorized distribution of multimedia content. It offers content protection and anti-piracy measures, maintaining content quality by embedding invisible information. This process involves inserting and extracting watermarks. We introduce a robust algorithm, combining discrete Haar wavelet transform (DHWT) and discrete cosine transform (DCT), yielding effective watermarking with high resistance to extraction without data loss. This combination of transforms represents a hybrid approach that we call HyDHWCT in this work. Evaluations reveal our approach’s superior accuracy compared to state-of-the-art methods. Our hardware watermarking solution excels in robustness and energy efficiency, even under diverse attack scenarios. FPGA and ASIC assessments show our HyDHWCT’s exceptional area and power performance, with the algorithm achieving a lossless watermark extraction (NC = 1), outperforming prior methods in accuracy-quality, and energy-, and area-savings (approximately (2.621times ) and (1.174times ), respectively). Accuracy-quality results confirm a perfect extraction rate (NC = 1), ensuring 100% accuracy in watermark extraction.","PeriodicalId":10227,"journal":{"name":"Circuits, Systems and Signal Processing","volume":"98 1","pages":""},"PeriodicalIF":2.3,"publicationDate":"2024-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142212280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Human Violence Detection in Videos Using Key Frame Identification and 3D CNN with Convolutional Block Attention Module 利用关键帧识别和带有卷积块注意力模块的 3D CNN 检测视频中的人类暴力行为

IF 2.3 3区工程技术

Circuits, Systems and Signal Processing Pub Date : 2024-08-13 DOI: 10.1007/s00034-024-02824-w

Venkatesh Akula, Ilaiah Kavati

{"title":"Human Violence Detection in Videos Using Key Frame Identification and 3D CNN with Convolutional Block Attention Module","authors":"Venkatesh Akula, Ilaiah Kavati","doi":"10.1007/s00034-024-02824-w","DOIUrl":"https://doi.org/10.1007/s00034-024-02824-w","url":null,"abstract":"In recent years, there has been an increase in demand for intelligent automatic surveillance systems to detect abnormal activities at various places, such as schools, hospitals, prisons, psychiatric centers, and public gatherings. The availability of video surveillance cameras in such places enables techniques for automatically identifying violent actions and alerting the authorities to minimize loss. Deep learning-based models, such as Convolutional Neural Networks (CNNs), have shown better performance in detecting violent activities by utilizing the spatiotemporal features of video frames. In this work, we propose a violence detection model based on 3D CNN, which employs a DenseNet architecture for enhanced spatiotemporal feature capture. First, the video’s redundant frames are discarded by identifying the key frames in the video. We exploit the Multi-Scale Structural Similarity Index Measure (MS-SSIM) technique to identify the key frames of the video, which contain significant information about the video. Key frame identification helps to reduce the complexity of the model. Next, the identified video key frames with the lowest MS-SSIM are forwarded to 3D CNN to extract spatiotemporal features. Furthermore, we exploit the Convolutional Block Attention Module (CBAM) to increase the representational capabilities of the 3D CNN. The results on different benchmark datasets show that the proposed violence detection method performs better than most of the existing methods. The source code for the proposed method is publicly available at https://github.com/venkateshakula19/violence-detection-using-keyframe-extraction-and-CNN-with-attention-CBAM","PeriodicalId":10227,"journal":{"name":"Circuits, Systems and Signal Processing","volume":"58 1","pages":""},"PeriodicalIF":2.3,"publicationDate":"2024-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142212283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A design approach of fractional model error compensator for fractional dynamical systems with polytopic uncertainty and disturbance 具有多态不确定性和扰动的分数动力系统的分数模型误差补偿器设计方法

IF 2.3 3区工程技术

Circuits, Systems and Signal Processing Pub Date : 2024-08-13 DOI: 10.1007/s00034-024-02813-z

Ahmed Haddi, Mohamed El Azzouzi, Mohamed Laabissi

{"title":"A design approach of fractional model error compensator for fractional dynamical systems with polytopic uncertainty and disturbance","authors":"Ahmed Haddi, Mohamed El Azzouzi, Mohamed Laabissi","doi":"10.1007/s00034-024-02813-z","DOIUrl":"https://doi.org/10.1007/s00034-024-02813-z","url":null,"abstract":"We present a novel design methodology for a fractional model error compensator (FMEC) that addresses the challenge of model errors in fractional dynamical systems with polytopic uncertainty and disturbances. The FMEC can effectively compensate for model errors, thereby enhancing the performance of control systems. This approach leverages a combination of (mathcal{H}_infty )-norm criteria and the Particle Swarm Optimization (PSO) algorithm to optimize the compensator design. The methodology integrates (mathcal{H}_infty )-norm criteria for robust performance evaluation and PSO for optimization. The proposed FMEC design is validated through numerical simulations conducted on a fractional dynamical system. These simulations demonstrate that the design successfully compensates for model errors and improves the overall performance of the control system. This study offers a practical solution for designing robust FMECs applicable in various engineering fields, particularly for systems susceptible to polytopic uncertainty and disturbances.","PeriodicalId":10227,"journal":{"name":"Circuits, Systems and Signal Processing","volume":"7 1","pages":""},"PeriodicalIF":2.3,"publicationDate":"2024-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142212285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

2D Second-Order Time–Frequency Synchrosqueezing Transform: For Non-stationary Signals Well-Localized Components Extraction and Separation 二维二阶时频同步变换：针对非稳态信号的良好定位成分提取与分离

IF 2.3 3区工程技术

Circuits, Systems and Signal Processing Pub Date : 2024-08-13 DOI: 10.1007/s00034-024-02823-x

Yumeng Chen, Juan Li

{"title":"2D Second-Order Time–Frequency Synchrosqueezing Transform: For Non-stationary Signals Well-Localized Components Extraction and Separation","authors":"Yumeng Chen, Juan Li","doi":"10.1007/s00034-024-02823-x","DOIUrl":"https://doi.org/10.1007/s00034-024-02823-x","url":null,"abstract":"The time–frequency analysis (TFA) method is an effective tool to separate and extract main components for non-stationary signals such as vibration signals and seismic signals, which are time-varying and affected by high noise. However, suffering from the Heisenberg uncertainty principle and cross terms of time–frequency result, conventional TFA methods usually produce vague time–frequency representations (TFRs). As a branch of the TFA method, current redistributive compressive transforms enable to generate clear TFR. However, these techniques are limited to a singular type of signal, which is not applicable to deal with complicated signals in production. In order to enhance the applicability and the time–frequency (TF) aggregation capability, this paper proposes a promoted TFA method 2D-FTSST2 based on the synchrosqueezing transform combining two-dimensional information of time and frequency domains. For an accurate IF estimate, we also define a time redistribution operator, which can describe strong time and frequency-varying signals. This algorithm not only provides a high-resolution decomposition of multicomponent signals but also enables to extract main features in noisy environments. Experiments on simulated signals and real data confirm the validity and effectiveness of the proposed algorithm.","PeriodicalId":10227,"journal":{"name":"Circuits, Systems and Signal Processing","volume":"25 1","pages":""},"PeriodicalIF":2.3,"publicationDate":"2024-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142212282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Order Reduction of z-Domain Interval Systems by Advanced Routh Approximation Method 用先进的 Routh 近似法减少 z 域区间系统的阶次

IF 2.3 3区工程技术

Circuits, Systems and Signal Processing Pub Date : 2024-08-07 DOI: 10.1007/s00034-024-02799-8

Praveen Kumar, Pankaj Rai, Amit Kumar Choudhary

引用次数: 0

Input–Output Scheduling and Control for Efficient FPGA Realization of Digit-Serial Multiplication Over Generic Binary Extension Fields 在通用二进制扩展字段上高效实现数串乘法的 FPGA 输入输出调度与控制

IF 2.3 3区工程技术

Circuits, Systems and Signal Processing Pub Date : 2024-08-07 DOI: 10.1007/s00034-024-02793-0

Dibakar Pradhan, Pramod Kumar Meher, Bimal Kumar Meher

{"title":"Input–Output Scheduling and Control for Efficient FPGA Realization of Digit-Serial Multiplication Over Generic Binary Extension Fields","authors":"Dibakar Pradhan, Pramod Kumar Meher, Bimal Kumar Meher","doi":"10.1007/s00034-024-02793-0","DOIUrl":"https://doi.org/10.1007/s00034-024-02793-0","url":null,"abstract":"In this paper, we propose an energy-efficient design of architecture for digit-serial multiplication over generic GF((2^m)), which could be used for different fields as and when required and to enhance the security by changing the fields. An efficient input scheduling scheme is proposed to reduce the required number of input pins and a digit extraction circuit for digit-serial multiplication. Besides, to reduce the dynamic power consumption, we have proposed a simple technique using an array of m AND gates that minimizes the output bit-switching. To study the impact of digit size, the digit-serial multipliers for (m=163) and 233 are synthesised by Xilinx Vivado for FPGA implementation. It is found that the required number of slices, power consumption, and energy per multiplication increase while the computational delay falls with the increase in digit size. Therefore, larger digit sizes could be considered only when fast multiplication is necessary. The array of AND gates for output bit control helps in reducing the dynamic power consumption and energy per multiplication, respectively, by 50.4% and 57.7% for (m=163) and (49.8%) and (51.8%), for (m=233), on average, for different digit sizes over the conventional least-significant-digit-first design.","PeriodicalId":10227,"journal":{"name":"Circuits, Systems and Signal Processing","volume":"16 1","pages":""},"PeriodicalIF":2.3,"publicationDate":"2024-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141949392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Optimal Design of Low-Power Ultra-Wideband Low-Noise Transconductance Amplifier in 0.18 µm CMOS 0.18 µm CMOS 低功耗超宽带低噪声跨导放大器的优化设计

IF 2.3 3区工程技术

Circuits, Systems and Signal Processing Pub Date : 2024-08-07 DOI: 10.1007/s00034-024-02803-1

W. Yasmeen, G. N. Swamy, K. Padma Priya

{"title":"Optimal Design of Low-Power Ultra-Wideband Low-Noise Transconductance Amplifier in 0.18 µm CMOS","authors":"W. Yasmeen, G. N. Swamy, K. Padma Priya","doi":"10.1007/s00034-024-02803-1","DOIUrl":"https://doi.org/10.1007/s00034-024-02803-1","url":null,"abstract":"A low-noise amplifier (LNA) is one of the most crucial components of a communication system. The current low-noise amplifier design faces challenges due to intrinsic noise sources in CMOS transistors and trade-offs to maximize gain and bandwidth. Hence the Optimal design of a low-power ultra-wideband low-noise transconductance amplifier in 0.18 µm CMOS is introduced to minimize the noise figure of the amplifier. Ultra wideband (UWB) signals cover a wide frequency range making it challenging to achieve good input and output matching across the entire band. Thus, Cascode inductive degenerative using pi matching network enhances input–output matching by providing impedance transformation, matching source impedance to low input impedance, and improving power transfer rate. However, the cascode configuration with pi matching offers superior performance over a wide frequency range, but it requires careful consideration of gain and noise figures. Therefore, a current reuse technique is utilized to improve gain and reduce noise figures by optimizing the distribution of bias currents and enhancing the overall performance of the amplifier. Furthermore, the main design challenge for LNAs is achieving high linearity in interference-filled environments. Hence novel Cascade inductive degenerative using T matching network addresses low-frequency signal interference by utilizing multiple amplifier stages for gain and high linearity. Thus, the result obtained showed that the proposed model outperforms the existing design with high gain of 17.7 dB, high input return loss of 10.6 dB, high FOM of 24.4 and low noise figures of 0.573 dB, thus improves the overall performance of the system.","PeriodicalId":10227,"journal":{"name":"Circuits, Systems and Signal Processing","volume":"22 1","pages":""},"PeriodicalIF":2.3,"publicationDate":"2024-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141949394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Composite State Tracking Control Protocol for Semi-Markovian Jump Systems with Time-Varying Delays 具有时变延迟的半马尔可夫跳跃系统的复合状态跟踪控制协议

IF 2.3 3区工程技术

Circuits, Systems and Signal Processing Pub Date : 2024-08-07 DOI: 10.1007/s00034-024-02773-4

Harshavarthini Shanmugam, Sakthivel Rathinasamy, Anusuya Sundaram, Mohammadzadeh Ardashir

引用次数: 0

Posture-Invariant Human Detection and Tracking for Outdoor Night-Time Surveillance 用于室外夜间监控的姿态不变人体检测与跟踪技术

IF 2.3 3区工程技术

Circuits, Systems and Signal Processing Pub Date : 2024-08-07 DOI: 10.1007/s00034-024-02808-w

Merzouk Younsi, Moussa Diaf, Patrick Siarry

{"title":"Posture-Invariant Human Detection and Tracking for Outdoor Night-Time Surveillance","authors":"Merzouk Younsi, Moussa Diaf, Patrick Siarry","doi":"10.1007/s00034-024-02808-w","DOIUrl":"https://doi.org/10.1007/s00034-024-02808-w","url":null,"abstract":"Human detection and tracking from infrared image sequences has received considerable attention in many practical applications, ranging from security and surveillance to automated health-care monitoring. However, most of the systems currently reported in the literature assume that humans are in an upright standing or walking posture in the monitored scene, which may not be true in some real-world surveillance scenarios, as humans can move in other abnormal postures, such as creeping and crawling. To overcome this limitation and enable human detection even in the presence of posture changes, this paper proposes a novel system based on locating human head–shoulder Ω-like part and two legs. For tracking purposes, a particle filter and an adaptive combination of different cues, namely spatial, intensity, texture and motion velocity are used. Then, to better describe the posture of the detected human and thus enable its effective recognition over time, three different features, namely Krawtchouk moments, chain code histograms and geometry-based features are first extracted, and then fed into a dendrogram-based support vector machine classifier for posture recognition. The results of posture recognition, in combination with the tracking information, are finally exploited to analyze the behavior of the detected human in the monitored scene. The proposed system was evaluated by performing extensive experiments using several infrared image sequences taken in a real outdoor nighttime environment. The obtained results are satisfactory and demonstrate the feasibility and effectiveness of the proposed system for the automatic detection of moving humans and the analysis of their behavior.","PeriodicalId":10227,"journal":{"name":"Circuits, Systems and Signal Processing","volume":"58 1","pages":""},"PeriodicalIF":2.3,"publicationDate":"2024-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141949391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0