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Chaotic methods for the papallel solution of linear systems 线性系统叠列解的混沌方法
Computing Systems in Engineering Pub Date : 1995-08-01 DOI: 10.1016/0956-0521(95)00046-1
Rafael Bru , Violeta Migallon , José Penadés
{"title":"Chaotic methods for the papallel solution of linear systems","authors":"Rafael Bru ,&nbsp;Violeta Migallon ,&nbsp;José Penadés","doi":"10.1016/0956-0521(95)00046-1","DOIUrl":"10.1016/0956-0521(95)00046-1","url":null,"abstract":"<div><p>Chaotic synchronous and asynchronous schemes based on two-stage methods to solve nonsingular linear systems are presented. The convergence of these schemes is studied either when the chaotic parameters become sufficiently large or when the matrix in question is monotone. The results are illustrated by computational experiments on a shared memory multiprocessor vector computer.</p></div>","PeriodicalId":100325,"journal":{"name":"Computing Systems in Engineering","volume":"6 4","pages":"Pages 385-390"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/0956-0521(95)00046-1","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88965943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Multisplitting iterative methods on fixed-size VLSI architectures 固定尺寸VLSI架构上的多重分裂迭代方法
Computing Systems in Engineering Pub Date : 1995-08-01 DOI: 10.1016/0956-0521(95)00036-4
Elena Papadopoulou, Yiannis Saridakis
{"title":"Multisplitting iterative methods on fixed-size VLSI architectures","authors":"Elena Papadopoulou,&nbsp;Yiannis Saridakis","doi":"10.1016/0956-0521(95)00036-4","DOIUrl":"10.1016/0956-0521(95)00036-4","url":null,"abstract":"<div><p>Multisplitting Iterative Methods is a parametrizable family of iterative methods capable of solving Large Linear Systems. They are formed by the proper weighted average of classical (or not) iterative schemes. Hence, they present a second level of inherent parallelism while, at the same time, they take advantage of the parallel hardware to decrease both the computational time and the number of iterations involved in the computation. The increasingly large size of linear systems and the consideration of realistically large, but fixed-size, VLSI architectures, for their solution, motivated this work. We design new fixed size VLSI modules, based on space-time partitioning techniques, to efficiently resolve the problems arising in the computation of an oversized iteration step.</p></div>","PeriodicalId":100325,"journal":{"name":"Computing Systems in Engineering","volume":"6 4","pages":"Pages 477-484"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/0956-0521(95)00036-4","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87331008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Multi-transputer systems with dynamic reconfiguration control based on the serial bus 基于串行总线的多机动态重构控制系统
Computing Systems in Engineering Pub Date : 1995-08-01 DOI: 10.1016/0956-0521(95)00031-3
T. Kalinowski, M. Thor, M. Tudruj
{"title":"Multi-transputer systems with dynamic reconfiguration control based on the serial bus","authors":"T. Kalinowski,&nbsp;M. Thor,&nbsp;M. Tudruj","doi":"10.1016/0956-0521(95)00031-3","DOIUrl":"10.1016/0956-0521(95)00031-3","url":null,"abstract":"<div><p>The paper presents new architectures of dynamically reconfigurable multi-transputer systems based on first generation transputers. Transputer link connections in the proposed systems are organized in crossbar switches on demand in the application program at run-time. Link connection reconfiguration control is based on transmission of control messages through the serial bus compatible with the transputer link protocol. The bus is built using the TRANSBUS controller proposed and designed by IRESTE University of Nantes.<sup>1</sup> Two dynamically reconfigurable multi-transputer architectures are discussed. The first one, called GARTS, is based on nine-worker transputer clusters with unrestricted dynamic link connectivity. Inter-cluster connections are also dynamically organized. The second architecture, called HP-MODTRANS, is based on three-transputer fully connected clusters with dynamically organized inter-cluster link connections. The structures and functional properties of both architectures are discussed. Then, analytical model for reconfiguration control communication overheads and some performance figures obtained using these models are presented for the discussed architectures.</p></div>","PeriodicalId":100325,"journal":{"name":"Computing Systems in Engineering","volume":"6 4","pages":"Pages 391-400"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/0956-0521(95)00031-3","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90782897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
The two-dimensional Navier-Stokes-Kuramoto-Sivashinsky equation on the Connection Machine 连接机上的二维Navier-Stokes-Kuramoto-Sivashinsky方程
Computing Systems in Engineering Pub Date : 1995-08-01 DOI: 10.1016/0956-0521(95)00027-5
S. Gama , U. Frisch
{"title":"The two-dimensional Navier-Stokes-Kuramoto-Sivashinsky equation on the Connection Machine","authors":"S. Gama ,&nbsp;U. Frisch","doi":"10.1016/0956-0521(95)00027-5","DOIUrl":"10.1016/0956-0521(95)00027-5","url":null,"abstract":"<div><p>The two-dimensional Navier-Stokes equations with a large scale instability of the Kuramoto-Sivashinsky type, describing marginally negative eddy viscosity situations, is simulated on a Connection Machine CM-2. Up to millions of time steps at the resolution 256<sup>2</sup> and tens of thousands at the resolution 1024<sup>2</sup> are performed. A linear growth phase, a disorganized inverse cascade phase and a structured vortical phase are successively observed. In the vortical phase monopolar and multipolar structures are proliferating and display strongly depleted nonlinearities.</p></div>","PeriodicalId":100325,"journal":{"name":"Computing Systems in Engineering","volume":"6 4","pages":"Pages 325-329"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/0956-0521(95)00027-5","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90710100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Debugging parallel programs using event graph manipulation 使用事件图操作调试并行程序
Computing Systems in Engineering Pub Date : 1995-08-01 DOI: 10.1016/0956-0521(95)00040-2
Siegfried Grabner, Jens Volkert
{"title":"Debugging parallel programs using event graph manipulation","authors":"Siegfried Grabner,&nbsp;Jens Volkert","doi":"10.1016/0956-0521(95)00040-2","DOIUrl":"10.1016/0956-0521(95)00040-2","url":null,"abstract":"<div><p>The need for more accurate results and larger problem sizes pushes the users in certain fields towards using supercomputing power. Besides problems with initial program development, another problem arises with debugging this kind of program. Debugging parallel programs is one of the hard tasks that users have to deal with when using parallel architectures. Where memory hot spots and bus contention are problems with shared memory architectures, nondeterminism arising from race conditions and the lack of a global clock are severe problems in using distributed memory architectures. We will discuss a new approach for detecting and/or studying concurrent events in distributed memory machines if race conditions occur in a certain program run. Through event graph manipulation the user can investigate whether wrong results may appear through different ordering of events.</p></div>","PeriodicalId":100325,"journal":{"name":"Computing Systems in Engineering","volume":"6 4","pages":"Pages 443-450"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/0956-0521(95)00040-2","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81810999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
An efficient parallel implementation of a least squares problem 最小二乘问题的有效并行实现
Computing Systems in Engineering Pub Date : 1995-08-01 DOI: 10.1016/0956-0521(95)00041-0
A.E.B. Ruano , P.J. Fleming , D.I. Jones
{"title":"An efficient parallel implementation of a least squares problem","authors":"A.E.B. Ruano ,&nbsp;P.J. Fleming ,&nbsp;D.I. Jones","doi":"10.1016/0956-0521(95)00041-0","DOIUrl":"10.1016/0956-0521(95)00041-0","url":null,"abstract":"<div><p>Least squares solutions are a very important problem, which appear in a broad range of disciplines (for instance, control systems, optimisation, statistics, signal processing). Our interest in this kind of problem lies in their use for training neural network controllers. We have recently proposed a new learning algorithm for training multilayer perceptrons, in which two least squares problems have to be solved in each iteration. As one of them constitutes the bulk of the computation of the learning algorithm, we have looked for efficient parallel solutions for least squares problems. For accuracy reasons, a QR algorithm was used to compute these steps of the learning algorithm. By modifying the sequence of operations that are performed by a known parallel solution for this type of problem, a boost in parallel efficiency was obtained. Extensive testing with different topologies and different router algorithms was conducted, enabling us to determine an optimal solution.</p></div>","PeriodicalId":100325,"journal":{"name":"Computing Systems in Engineering","volume":"6 4","pages":"Pages 313-318"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/0956-0521(95)00041-0","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87245009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A heterogeneous computer vision architecture: Implementation issues 异构计算机视觉体系结构:实现问题
Computing Systems in Engineering Pub Date : 1995-08-01 DOI: 10.1016/0956-0521(95)00029-1
Henrique Dinis Santos, JoséCarlos Ramalho, João Miguel Fernandes, Alberto José Proença
{"title":"A heterogeneous computer vision architecture: Implementation issues","authors":"Henrique Dinis Santos,&nbsp;JoséCarlos Ramalho,&nbsp;João Miguel Fernandes,&nbsp;Alberto José Proença","doi":"10.1016/0956-0521(95)00029-1","DOIUrl":"10.1016/0956-0521(95)00029-1","url":null,"abstract":"<div><p>The prototype of a heterogeneous architecture is currently being built. The architecture is aimed at video-rate computing and is based on a message passing MIMD topology at the top level—transputer based—and on VLSI associative processor arrays (APA, SIMD structure) for low level image processing tasks. The APA structure is implemented through a set of 4 VLSI chips (GLiTCH) containing 64 1-bit processing elements each. This communication addresses some issues concerning the implementation of the first prototype, namely those related to: </p><ul><li><span>•</span><span><p>—the design and integration of the APA controller unit, which provides the required interface between the APA, the MIMD topology and the video image interface:</p></span></li><li><span>•</span><span><p>—the evaluation of the GLiTCH chip through an emulator based on transputers and fast programmable devices; the emulator was designed to be flexible enough to evaluate later modifications to the GLiTCH design;</p></span></li><li><span>•</span><span><p>—the design of an integrated set of software development tools containing a structured editor—syntax oriented, with a visual interface/programming interface—and a cross compiler and debugger.</p></span></li></ul></div>","PeriodicalId":100325,"journal":{"name":"Computing Systems in Engineering","volume":"6 4","pages":"Pages 401-408"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/0956-0521(95)00029-1","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72782050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Numerical simulation of liquid-liquid agitated dispersions on the VAX 6520/VP 液-液搅拌分散体在VAX 6520/VP上的数值模拟
Computing Systems in Engineering Pub Date : 1995-08-01 DOI: 10.1016/0956-0521(95)00047-X
L.M. Ribeiro , P.F.R. Regueiras , M.M.L. Guimarães , J.J.C. Cruz-Pinto
{"title":"Numerical simulation of liquid-liquid agitated dispersions on the VAX 6520/VP","authors":"L.M. Ribeiro ,&nbsp;P.F.R. Regueiras ,&nbsp;M.M.L. Guimarães ,&nbsp;J.J.C. Cruz-Pinto","doi":"10.1016/0956-0521(95)00047-X","DOIUrl":"10.1016/0956-0521(95)00047-X","url":null,"abstract":"<div><p>This work began as a study of the implementation of a liquid-liquid hydrodynamic and mass transfer simulation algorithm on the VAX 6000 model 520 vector processor. A scalar code developed by Riberio <em>et al.</em><sup>3</sup> has proved adequate and accurate to describe the transient and the limiting hydrodynamic steady-state, either of a continuous or of a batch liquid-liquid contactor; it also may be extended to predict the mass transfer performance of this type of system. Using this pre-existing FORTRAN code, we describe some techniques for modifying it in order to take advantage of the VAX 6000 vector architecture. The main thrust of this investigation is to identify the characteristics of the VAX vector processor that affect performance, and to show how that performance information can be used to build optimized algorithms. The nature of the modifications made to the algorithm and their effect on the overall computation time are reported for two types of changes: scalar optimization and vectorization.</p></div>","PeriodicalId":100325,"journal":{"name":"Computing Systems in Engineering","volume":"6 4","pages":"Pages 465-469"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/0956-0521(95)00047-X","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77693601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
On writing a router for message passing in a transputer network 关于编写一个路由器用于在计算机网络中传递消息
Computing Systems in Engineering Pub Date : 1995-08-01 DOI: 10.1016/0956-0521(95)00038-0
A.Augusto Sousa, F.Nunes Ferreira
{"title":"On writing a router for message passing in a transputer network","authors":"A.Augusto Sousa,&nbsp;F.Nunes Ferreira","doi":"10.1016/0956-0521(95)00038-0","DOIUrl":"10.1016/0956-0521(95)00038-0","url":null,"abstract":"<div><p>In a distributed memory MIMD parallel machine, the efficient communication between processes/processors, through messages, is an important task to be handled by the programmer. Because the number of inter-processor connections is limited, the communication between any two processors is made by passing the messages through several other processors and then, a problem of messages routing appears. For dedicated systems, special architectures can be defined simplifying the problem but, if an environment constituting a basis for general applications development is desired, the problem is more serious due to the deadlock possibility. A general router, able to avoid the problem, becomes then a very important tool for software development in parallel architectures. We have been defining a development platform, based on a network of Transputers and written in OCCAM, for image synthesis applications. This paper reports our efforts in writing different versions of routers, based on two different strategies, and justifies the choice of an efficient one to integrate in the platform.</p></div>","PeriodicalId":100325,"journal":{"name":"Computing Systems in Engineering","volume":"6 4","pages":"Pages 471-476"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/0956-0521(95)00038-0","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85221394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Operating system support for parallel computation 操作系统支持并行计算
Computing Systems in Engineering Pub Date : 1995-08-01 DOI: 10.1016/0956-0521(95)00044-5
Francisco Soares de Moura
{"title":"Operating system support for parallel computation","authors":"Francisco Soares de Moura","doi":"10.1016/0956-0521(95)00044-5","DOIUrl":"10.1016/0956-0521(95)00044-5","url":null,"abstract":"<div><p>Parallel systems are not necessarily special-purpose machines. At present, most departmental servers already resort to shared memory multiprocessing as a means to increase performance, while a network of workstations can also be regarded as a distributed memory parallel system. This paper examines the support offered by the operating system to exploit such parallelism. After discussing the design of multi-threaded programs in a Unix environment, a comparison is made with their distributed counterparts. Some performance figures obtained on a SparcCenter 2000 multiprocessor. on a network of workstations and on a transputer-based system are presented.</p></div>","PeriodicalId":100325,"journal":{"name":"Computing Systems in Engineering","volume":"6 4","pages":"Pages 307-312"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/0956-0521(95)00044-5","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90799899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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