A heterogeneous computer vision architecture: Implementation issues

Computing Systems in Engineering Pub Date : 1995-08-01 DOI:10.1016/0956-0521(95)00029-1

Henrique Dinis Santos, JoséCarlos Ramalho, João Miguel Fernandes, Alberto José Proença

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引用次数: 2

Abstract

The prototype of a heterogeneous architecture is currently being built. The architecture is aimed at video-rate computing and is based on a message passing MIMD topology at the top level—transputer based—and on VLSI associative processor arrays (APA, SIMD structure) for low level image processing tasks. The APA structure is implemented through a set of 4 VLSI chips (GLiTCH) containing 64 1-bit processing elements each. This communication addresses some issues concerning the implementation of the first prototype, namely those related to:

•
—the design and integration of the APA controller unit, which provides the required interface between the APA, the MIMD topology and the video image interface:
•
—the evaluation of the GLiTCH chip through an emulator based on transputers and fast programmable devices; the emulator was designed to be flexible enough to evaluate later modifications to the GLiTCH design;
•
—the design of an integrated set of software development tools containing a structured editor—syntax oriented, with a visual interface/programming interface—and a cross compiler and debugger.

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异构计算机视觉体系结构:实现问题

异构体系结构的原型目前正在构建中。该体系结构旨在视频速率计算，并基于顶层的消息传递MIMD拓扑(基于转发器)和用于低级图像处理任务的VLSI关联处理器阵列(APA, SIMD结构)。APA结构通过一组4个VLSI芯片(GLiTCH)实现，每个芯片包含64个1位处理元件。本通信解决了有关第一个原型实现的一些问题，即与以下相关的问题:•- APA控制器单元的设计和集成，它提供了APA, MIMD拓扑和视频图像接口之间所需的接口;•-通过基于转换器和快速可编程设备的模拟器评估GLiTCH芯片;模拟器设计得足够灵活，可以评估GLiTCH设计的后续修改;•设计一套集成的软件开发工具，其中包含结构化编辑器-面向语法，具有可视化界面/编程界面-以及交叉编译器和调试器。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Computing Systems in Engineering

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