Henrique Dinis Santos, JoséCarlos Ramalho, João Miguel Fernandes, Alberto José Proença
{"title":"异构计算机视觉体系结构:实现问题","authors":"Henrique Dinis Santos, JoséCarlos Ramalho, João Miguel Fernandes, Alberto José Proença","doi":"10.1016/0956-0521(95)00029-1","DOIUrl":null,"url":null,"abstract":"<div><p>The prototype of a heterogeneous architecture is currently being built. The architecture is aimed at video-rate computing and is based on a message passing MIMD topology at the top level—transputer based—and on VLSI associative processor arrays (APA, SIMD structure) for low level image processing tasks. The APA structure is implemented through a set of 4 VLSI chips (GLiTCH) containing 64 1-bit processing elements each. This communication addresses some issues concerning the implementation of the first prototype, namely those related to: </p><ul><li><span>•</span><span><p>—the design and integration of the APA controller unit, which provides the required interface between the APA, the MIMD topology and the video image interface:</p></span></li><li><span>•</span><span><p>—the evaluation of the GLiTCH chip through an emulator based on transputers and fast programmable devices; the emulator was designed to be flexible enough to evaluate later modifications to the GLiTCH design;</p></span></li><li><span>•</span><span><p>—the design of an integrated set of software development tools containing a structured editor—syntax oriented, with a visual interface/programming interface—and a cross compiler and debugger.</p></span></li></ul></div>","PeriodicalId":100325,"journal":{"name":"Computing Systems in Engineering","volume":"6 4","pages":"Pages 401-408"},"PeriodicalIF":0.0000,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/0956-0521(95)00029-1","citationCount":"2","resultStr":"{\"title\":\"A heterogeneous computer vision architecture: Implementation issues\",\"authors\":\"Henrique Dinis Santos, JoséCarlos Ramalho, João Miguel Fernandes, Alberto José Proença\",\"doi\":\"10.1016/0956-0521(95)00029-1\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p>The prototype of a heterogeneous architecture is currently being built. The architecture is aimed at video-rate computing and is based on a message passing MIMD topology at the top level—transputer based—and on VLSI associative processor arrays (APA, SIMD structure) for low level image processing tasks. The APA structure is implemented through a set of 4 VLSI chips (GLiTCH) containing 64 1-bit processing elements each. This communication addresses some issues concerning the implementation of the first prototype, namely those related to: </p><ul><li><span>•</span><span><p>—the design and integration of the APA controller unit, which provides the required interface between the APA, the MIMD topology and the video image interface:</p></span></li><li><span>•</span><span><p>—the evaluation of the GLiTCH chip through an emulator based on transputers and fast programmable devices; the emulator was designed to be flexible enough to evaluate later modifications to the GLiTCH design;</p></span></li><li><span>•</span><span><p>—the design of an integrated set of software development tools containing a structured editor—syntax oriented, with a visual interface/programming interface—and a cross compiler and debugger.</p></span></li></ul></div>\",\"PeriodicalId\":100325,\"journal\":{\"name\":\"Computing Systems in Engineering\",\"volume\":\"6 4\",\"pages\":\"Pages 401-408\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://sci-hub-pdf.com/10.1016/0956-0521(95)00029-1\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Computing Systems in Engineering\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/0956052195000291\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Computing Systems in Engineering","FirstCategoryId":"1085","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/0956052195000291","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A heterogeneous computer vision architecture: Implementation issues
The prototype of a heterogeneous architecture is currently being built. The architecture is aimed at video-rate computing and is based on a message passing MIMD topology at the top level—transputer based—and on VLSI associative processor arrays (APA, SIMD structure) for low level image processing tasks. The APA structure is implemented through a set of 4 VLSI chips (GLiTCH) containing 64 1-bit processing elements each. This communication addresses some issues concerning the implementation of the first prototype, namely those related to:
•
—the design and integration of the APA controller unit, which provides the required interface between the APA, the MIMD topology and the video image interface:
•
—the evaluation of the GLiTCH chip through an emulator based on transputers and fast programmable devices; the emulator was designed to be flexible enough to evaluate later modifications to the GLiTCH design;
•
—the design of an integrated set of software development tools containing a structured editor—syntax oriented, with a visual interface/programming interface—and a cross compiler and debugger.
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