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International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications最新文献

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Object Oriented Programming Paradigms for the VHDL 面向对象编程范型的VHDL
International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications Pub Date : 2004-08-30 DOI: 10.1007/978-3-540-30117-2_139
J. Borgosz
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引用次数: 0
Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors 便携式可重构协处理器虚拟内存窗口中的动态预取
International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications Pub Date : 2004-08-30 DOI: 10.1007/978-3-540-30117-2_61
M. Vuletic, L. Pozzi, P. Ienne
{"title":"Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors","authors":"M. Vuletic, L. Pozzi, P. Ienne","doi":"10.1007/978-3-540-30117-2_61","DOIUrl":"https://doi.org/10.1007/978-3-540-30117-2_61","url":null,"abstract":"","PeriodicalId":93570,"journal":{"name":"International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications","volume":"150 1","pages":"596-605"},"PeriodicalIF":0.0,"publicationDate":"2004-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77384657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays 流水线对现场可编程门阵列每次操作能量的影响
International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications Pub Date : 2004-08-30 DOI: 10.1007/978-3-540-30117-2_73
S. Wilton, Su-Shin Ang, W. Luk
{"title":"The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays","authors":"S. Wilton, Su-Shin Ang, W. Luk","doi":"10.1007/978-3-540-30117-2_73","DOIUrl":"https://doi.org/10.1007/978-3-540-30117-2_73","url":null,"abstract":"","PeriodicalId":93570,"journal":{"name":"International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications","volume":"74 1","pages":"719-728"},"PeriodicalIF":0.0,"publicationDate":"2004-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85959559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 116
An Evolvable Hardware Tutorial 可进化的硬件教程
International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications Pub Date : 2004-08-30 DOI: 10.1007/978-3-540-30117-2_83
J. Tørresen
{"title":"An Evolvable Hardware Tutorial","authors":"J. Tørresen","doi":"10.1007/978-3-540-30117-2_83","DOIUrl":"https://doi.org/10.1007/978-3-540-30117-2_83","url":null,"abstract":"","PeriodicalId":93570,"journal":{"name":"International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications","volume":"83 1","pages":"821-830"},"PeriodicalIF":0.0,"publicationDate":"2004-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73392748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
Real Environments Image Labelling Based on Reconfigurable Architectures 基于可重构架构的真实环境图像标记
International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications Pub Date : 2004-08-30 DOI: 10.1007/978-3-540-30117-2_138
J. Chamizo, Andrés Fuster Guilló, J. A. López
{"title":"Real Environments Image Labelling Based on Reconfigurable Architectures","authors":"J. Chamizo, Andrés Fuster Guilló, J. A. López","doi":"10.1007/978-3-540-30117-2_138","DOIUrl":"https://doi.org/10.1007/978-3-540-30117-2_138","url":null,"abstract":"","PeriodicalId":93570,"journal":{"name":"International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications","volume":"77 1","pages":"1104-1106"},"PeriodicalIF":0.0,"publicationDate":"2004-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76615969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Java Technology in an FPGA FPGA中的Java技术
International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications Pub Date : 2004-08-30 DOI: 10.1007/978-3-540-30117-2_99
Martin Schoeberl
{"title":"Java Technology in an FPGA","authors":"Martin Schoeberl","doi":"10.1007/978-3-540-30117-2_99","DOIUrl":"https://doi.org/10.1007/978-3-540-30117-2_99","url":null,"abstract":"","PeriodicalId":93570,"journal":{"name":"International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications","volume":"125 1","pages":"917-921"},"PeriodicalIF":0.0,"publicationDate":"2004-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76292362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
An FPGA Based Coprocessor for the Classification of Tissue Patterns in Prostatic Cancer 基于FPGA的前列腺癌组织模式分类协处理器
International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications Pub Date : 2004-08-30 DOI: 10.1007/978-3-540-30117-2_78
M. Tahir, A. Bouridane, F. Kurugollu
{"title":"An FPGA Based Coprocessor for the Classification of Tissue Patterns in Prostatic Cancer","authors":"M. Tahir, A. Bouridane, F. Kurugollu","doi":"10.1007/978-3-540-30117-2_78","DOIUrl":"https://doi.org/10.1007/978-3-540-30117-2_78","url":null,"abstract":"","PeriodicalId":93570,"journal":{"name":"International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications","volume":"11 1","pages":"771-780"},"PeriodicalIF":0.0,"publicationDate":"2004-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75892124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Power-Driven Design Partitioning 电源驱动设计分区
International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications Pub Date : 2004-08-30 DOI: 10.1007/978-3-540-30117-2_75
R. Mukherjee, S. Memik
{"title":"Power-Driven Design Partitioning","authors":"R. Mukherjee, S. Memik","doi":"10.1007/978-3-540-30117-2_75","DOIUrl":"https://doi.org/10.1007/978-3-540-30117-2_75","url":null,"abstract":"","PeriodicalId":93570,"journal":{"name":"International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications","volume":"76 1","pages":"740-750"},"PeriodicalIF":0.0,"publicationDate":"2004-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80900198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Area*Time Optimized Hogenauer Channelizer Design Using FPL Devices 使用FPL器件的面积*时间优化Hogenauer通道设计
International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications Pub Date : 2004-08-30 DOI: 10.1007/978-3-540-30117-2_40
U. Meyer-Bäse, S. Rao, J. Ramírez, Antonio García
{"title":"Area*Time Optimized Hogenauer Channelizer Design Using FPL Devices","authors":"U. Meyer-Bäse, S. Rao, J. Ramírez, Antonio García","doi":"10.1007/978-3-540-30117-2_40","DOIUrl":"https://doi.org/10.1007/978-3-540-30117-2_40","url":null,"abstract":"","PeriodicalId":93570,"journal":{"name":"International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications","volume":"140 1","pages":"384-393"},"PeriodicalIF":0.0,"publicationDate":"2004-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83024919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Distribution of Bitstream-Level IP Cores for Functional Evaluation Using FPGAs 用fpga进行功能评估的位流级IP核的分布
International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications Pub Date : 2004-08-30 DOI: 10.1007/978-3-540-30117-2_71
Rawat Siripokarpirom
{"title":"Distribution of Bitstream-Level IP Cores for Functional Evaluation Using FPGAs","authors":"Rawat Siripokarpirom","doi":"10.1007/978-3-540-30117-2_71","DOIUrl":"https://doi.org/10.1007/978-3-540-30117-2_71","url":null,"abstract":"","PeriodicalId":93570,"journal":{"name":"International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications","volume":"57 1","pages":"700-709"},"PeriodicalIF":0.0,"publicationDate":"2004-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89569445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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